文档资料 许可 在线购买 下载 全部页面 技术资料 产品型号

主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买

器件   |   设计软件   |   IP   |   设计服务   |   开发套件及配件   |   资料

IP产品    嵌入式处理器    接口与外设           外设           PCI           PCI Express           Memory Controllers           USB           PCMCIA           Ethernet           I2C           CAN           PowerPC Bus           HyperTransport           RapidIO           SerialLite           Additional Functions           Consortiums           资料    DSP    通信     About IP       运用IP进行设计       IP认证       系统设计       申请IP     IP界合作伙伴       AMPP计划       AMPP核合作伙伴

主页 > 产品 > IP > 接口与外设 > Memory Controllers > SDR SDRAM Controller 打印此页 订阅电邮新闻 SDR SDRAM Controller from Northwest Logic, Inc. Features High-performance access logic with read and write queuing enables the highest possible throughput for all burst length (BL) settings: BL1, BL2, BL4, and BL8 Pipelined design enables high clock rates with minimal routing constraints Bank management logic monitors status of each SDRAM bank (up to 16 banks monitored)—banks only opened or closed when necessary, minimizing access delays Run-time configurable timing parameters: tCL, tRC, tRCD, tRP, tMRD, tRRD, and tREFC Supports auto-precharge option, enabling low random access latencies Supports SDRAM self-refresh and power-down modes Run-time configurable memory settings (i.e., row bits, column bits, and bank bits) Automatically generates initialization and refresh sequences Supports all standard SDRAM and DIMM devices Available with multi-port front-end option - provides eight user-port interfaces into the controller with command reordering, extended burst size, and memory test functions Optional error correction coding (ECC), read-modify-write, and multi-burst add-on modules available Source code license available (VHDL or Verilog HDL) Fast response, expert technical support provided by intellectual property (IP) designers Block Diagram Figure 1 shows the block diagram for the single data rate (SDR) SDRAM controller. Figure 1. Block Diagram for the SDR SDRAM Controller View Full Size Description Northwest Logic's SDR SDRAM controller provides a high-performance interface to SDR SDRAM devices. The controller is optimized to achieve high-performance, high-frequency operation with minimal constraints. Bank management techniques are used to monitor the status of each SDR SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 16 banks can be managed at one time. Access cascading is also supported, enabling read or write requests to be chained together. This results in no delay between requests, enabling up to 100 percent memory throughput for sequential accesses (not including refresh). A simple local interface is provided for easy integration with other device logic such as microcontroller buses and FIFO interfaces. The SDR SDRAM controller is provided with run-time programmable configuration ports for all timing parameters (CAS Latency, tRC, tRAS, tRCD, tRP, tMRD, tRRD, tXSNR, tREFC, tRFC, and tWR) as well as memory configuration settings. These inputs ensure compatibility with virtually any SDR SDRAM configuration. The SDR SDRAM controller core is available with an optional multi-port, front-end module which provides eight user-port interfaces into the controller. This module arbitrates between the various ports and provides user-selectable priority levels for each port. The multi-port, front-end module can perform command reordering to achieve optimal SDRAM bandwidth. The multi-port, front-end module also includes an extended burst interface and a built-in memory test module. The SDR SDRAM controller core is also available with optional ECC and read-modify-write modules. Device Utilization Example Table 1 lists the typical device utilization results for the controller. Table 1. Typical Device Utilization for the SDR SDRAM Controller Supported Altera® Devices Speed Grade Utilization Logic Elements Performance (fMAX) Parameter Setting Stratix® II/Stratix II GX -5 1,100 167 MHz Contact Northwest Logic Stratix/Stratix GX -6 1,100 167 MHz Contact Northwest Logic Cyclone® II -7 1,100 167 MHz Contact Northwest Logic Cyclone -7 1,100 133 MHz Contact Northwest Logic  Deliverables Core (netlist or source code) Comprehensive Verification Suite (source code) Complete documentation Expert technical support and maintenance updates Contact Information For additional information, contact Northwest Logic at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800, x309 Fax: (503) 533-5900 Email: ip@nwlogic.com URL: www.nwlogic.com 给本页评分

请填写反馈意见

主页 | 产品 | 支持 | 最终市场 | 技术中心 | 教育与活动 | 公司介绍 | 在线购买  器件 | 设计软件 | IP | 设计服务 | 开发套件及配件 | 资料  联系我们 | 站点帮助 | 网站导航 | 个人信息 | 法律申明  Copyright © 1995-2008 Altera International Limited, 香港九龙观塘观塘道388号创纪之城1期1座9楼11-18室 Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus和MegaCore是Altera公司的商标。