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PCI Express Compiler: x1, x4, and x8 MegaCore Functions

from Altera Corporation

Download Free Evaluation



OpenCore Plus Support
I-Test



Features

  • Feature rich
    • Hard intellectual property (IP) compliant with PCI Express Base Specification 2.0 and 1.1  with x1, x4, and x8 lane support for endpoint and root port applications
    • Configurable maximum payload
    • Optional end-to-end cyclic redundancy code (ECRC) generation/checking and advanced error reporting (AER)
  • Ease of use
    • Huge on-chip resource savings with hard IP
    • No license required for hard IP
    • Shorter compile times with hard IP
    • Embedded memory buffers in hard IP ease timing closure issues
    • Multiple example designs to jump start your designs
  • Support for soft IP on Altera's PCI Express Development Kit, Stratix® II GX Edition, and Altera's Arria® GX FPGA Development Kit

General Description

The PCI Express Compiler generates customized PCI Express MegaCore® functions that you can use to design PCI Express endpoints, including nontransparent bridges or truly unique designs combining multiple PCI Express components in a single Altera® device. The soft IP variant of the PCI Express MegaCore function is PCI Express Base Specification Revision 1.1 and PCI Express Base Specification Revision 1.0a compliant. The hard IP variant of the PCI Express MegaCore function is PCI Express Base Specification Revision 2.0 and 1.1 compliant.  

These popular PCI Express MegaCore functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. Also, the MegaCore functions are flexible and parameterizable, allowing customization for your specific needs. As an example, the MegaCore functions support a configurable payload, a configurable retry buffer, and optional support for high-reliability features like end-to-end cyclic redundancy code generation/checking and AER.

There are a number of deliverables available to facilitate the easy adoption and integration of the IP core into your design. The PCI Express Compiler includes an endpoint testbench that incorporates a simple root-port bus functional model (BFM) and multiple endpoint example designs. You can use these example designs, available in clear-text source-code (VHDL) and Verilog (HDL), as references to kick-start your design while the simple root-port BFM is geared to provide an "out of the box" PCI Express experience.

To facilitate easy system integration, the soft IP core also supports SOPC Builder for x1 and x4 applications. Further, to provide an easy timing closure flow, the IP core supports incremental compilation. Using the open-source incremental compilation module, once you have configured the highly parameterizable IP core, you can lock down the placement and routing of the IP core to preserve the timing while working on the back-end application logic.

Figure 1 shows a high level block diagram of the PCI Express hard IP block.

Figure 1. PCI Express Hard IP Block


View Full Size

IP Evaluation

Use the Altera OpenCore Plus Evaluation to test drive the soft IP core. For more information on OpenCore Plus hardware evaluation using the PCI Express Compiler MegaCore function, see AN 320: OpenCore Plus Evaluation of Megafunctions (PDF).

Performance

Typical expected performance and utilization figures for this core are provided in the PCI Express Compiler User Guide (PDF).

I-Tested

Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

Altera has performed significant hardware testing of the PCI Express x1, x4, and x8 soft IP MegaCore functions to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCI Express switch chips, and embedded microprocessors. Additionally, these MegaCore functions were tested at the PCI-SIG compliance workshops and passed with extremely high-quality results, including passing 100 percent of the PCI-SIG gold tests.

Technical Support

For technical support on these MegaCore functions, please visit the Altera mySupport online issue tracking system. You may also search for related topics on these functions in the Altera Solutions Database.

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