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主页 > 产品 > IP > 接口与外设 > PCI Express > x1, x4, x8 PCI Express Complete Cores 打印此页 订阅电邮新闻 x1, x4, x8 PCI Express Complete Cores from Northwest Logic, Inc. Features Combines Northwest Logic's PCI Express core and PCI Express back-end module for a complete, easy-to-use PCI Express solution Built-in high-performance, multi-channel DMA engine and simple target and register interfaces Available in x1, x4, x8 lane configurations Supports integrated or external discrete PCI Express PHYs Flexible data buffer sizing Complete error-handling support Comprehensive status port provides a wealth of diagnostic information that can be used for system-level debug and link stability monitoring Push-button timing achieved with minimal routing constraints Provided with a comprehensive source code PCI Express verification suite Customization and integration services available PCI Express base specification revision 1.1 compliant Available with development boards Core source code available Fully validated, including PCI-Sig, nSys, NVS, Catalyst SpekChek, and Lecroy CTS certification Available with Windows and Linux driver Available with GUI for Windows Included with reference design Fast response and expert technical support provided by experienced Northwest Logic IP designers  Block Diagram Figure 1 shows the block diagram for the megafunction. Figure 1. Block Diagram of the Megafunction Description The Northwest Logic PCI Express Complete core combines the PCI Express core and PCI Express back-end module, creating a complete, easy-to-use PCI Express solution. The PCI Express back-end functionality implements a complete back-end design that includes: High-performance, multi-channel DMA engine that can be easily connected to SDRAM and other data sources Complete target interface including packet decoding and generation of read completions while providing a simple user interface Very simple, fixed-timing register interface for connection to user's registers Using the PCI Express Complete Core eliminates the need for developing and implementing a separate back-end module, significantly reducing development time and risk The PCI Express back-end functionality can also be licensed separately in source code, enabling you to customize it to your specific requirements. The core is provided with PCI Express verification suite that emulates a root complex device enabling end-to-end simulation of a PCI Express design prior to use in hardware. The core has been extensively verified through ASIC-level test methodologies and has been integrated in a wide variety of applications. Also available from Northwest Logic are PCI Express development boards that you can use to quickly prototype a complete PCI Express system. The PCI Express reference design, driver, and GUI are provided with the board. Northwest Logic also provides customization and integration services to produce complete designs or sub-systems. Device Utilization and Performance Table 1 shows the typical device utilization results for the megafunction. Table 1. Typical Device Utilization for the Megafunction Supported Altera® Devices Speed Grade Utilization Logic Elements Performance (fMAX) Parameter Settings Stratix® II, Stratix II GX -5 12,500 x1 Core 17,000 x4 Core 23,000 x8 Core Internal (GX) or external PHY 125 MHz Contact Northwest Logic Stratix, Stratix GX -6 12,500 x1 Core 17,000 x4 Core 23,000 x8 Core Internal (GX) or external PHY 125 MHz Contact Northwest Logic Cyclone® II -5 12,500 x1 Core 21,000 - External PHY 125 MHz Contact Northwest Logic Cyclone -6 12,500 x1 Core 21,000 - External PHY 125 MHz Contact Northwest Logic Deliverables Core (netlist or source code) Comprehensive verification suite (source code) Complete documentation Expert technical support and maintenance updates Contact Information For additional information, contact Northwest Logic, Inc. at: Northwest Logic, Inc. 1100 NW Compton Drive, Ste. 100 Beaverton, OR 97006 Tel: (503) 533-5800, x309 Fax: (503) 533-5900 E-mail: ip@nwlogic.com URL: www.nwlogic.com/ 给本页评分

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