PCI32 Nios Target MegaCore Function
from Altera Corporation
Features
- Interface between the PCI bus and the Nios soft core embedded processor
- PCI 32-bit, 33-MHz master/target interface with host bridge capability
- Application programming interface (API) supplied for the Nios soft core embedded processor
- Behavioral RTL models for simulation in VHDL and Verilog HDL simulators
- Direct memory access (DMA) directly from FIFO buffers to PCI memory
- Messaging registers generate interrupts to Nios and PCI peripherals
- Easy-to-use wizard-driven interface that allows you to customize your application
- PCI testbench with the following features:
- Easy-to-use simulation environment for any standard VHDL or Verilog HDL simulator
- Open source VHDL and Verilog HDL files
- Flexible PCI bus functional model to verify your application that uses the PCI32 Nios Target MegaCore function
- Simulates all basic PCI transactions including memory reads/writes, I/O reads/writes, and configuration reads/writes
- Reference design suitable for simulation
General Description
The Altera® PCI32 Nios™ Target MegaCore® function connects a peripheral component interconnect (PCI) bus to the Nios soft core embedded processor system via the Avalon™ bus (see Figure 1). The Avalon bus is an Altera parameterized interface bus, which is a set of predefined signal types that connects one or more intellectual property (IP) blocks. For example, the Nios soft core embedded processor uses the Avalon bus to interconnect the CPU, peripherals, memory, and external I/O ports.
PCI32 Nios Target MegaCore Function
For more information on the Nios soft core embedded processor system, refer to the Nios documentation, which is supplied with the Nios development kit.
The PCI32 Nios Target MegaCore function comprises a 32-bit Nios target on one side and a 32-bit, 33-MHz PCI master/target on the other side.
The PCI32 Nios Target MegaCore function uses the established Altera PCI MegaCore function technology. The core is a Nios peripheral, which you can instantiate into your embedded processor system using the SOPC Builder. The core can be used as a master or target on the PCI bus, and can be parameterized to act as a PCI host bridge.
OpenCore Hardware Evaluation
The OpenCore feature lets you test-drive Altera® MegaCore functions for free using the Quartus II software. You can verify the functionality of a MegaCore function quickly and easily, as well as evaluate its size and speed before making a purchase decision. However, you cannot generate device programming files.
Performance
Table 1 shows the required speed and estimated gate count in Stratix and APEX 20KE devices.
| Performance Note (1) |
| Device |
LEs |
Memory |
fMAX (MHz) |
| Stratix |
2,624 |
2 |
33 |
| APEX 20KE |
2,839 |
4 |
33 |
Note:
- The numbers for the logic elements (LEs) and embedded system blocks (ESBs) are approximate as of January 2003
Licensing
A license is not required to perform the following trial operations using your own custom logic:
- Instantiation
- Place-and-route
- Static timing analysis
- Simulation on a third-party simulator
When you are ready to generate programming files, you need to obtain licenses through your local Altera sales representative.
Technical Support
For technical support on this MegaCore function, please visit the Altera mySupport on-line issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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