from Altera Corporation
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Features
- Contains 32-bit PCI master/target, 32-bit PCI target, 64-bit PCI master/target, 64-bit PCI target MegaCore® functions
- Fully compliant with the timing and functional requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0
- Extensively tested in hardware
- Easy SOPC Builder-ready integration using the general-purpose, full-featured bridge
- Intellectual property (IP) functional simulation models provide cycle-accurate behavioral simulations in industry-standard Verilog HDL and VHDL simulation tools
- Open-source PCI testbench provides flexible PCI bus functional models to verify Altera® PCI MegaCore function-based applications in industry-standard Verilog HDL and VHDL simulation tools
- Reference designs for popular functionality implemented on the local side of the PCI MegaCore functions, including direct memory access (DMA) engines, datapath FIFO architectures, and SDRAM interfaces
Description
Altera's PCI Compiler provides a complete, easy-to-use solution for implementing a PCI interface with Altera devices. The PCI Compiler contains the Altera pci_mt64, pci_t64, pci_mt32, and pci_t32 MegaCore functions and supports both SOPC Builder and MegaWizard® Plug-In Manager design flows. The SOPC Builder design flow allows you to quickly and easily implement a PCI interface into your design. Whether your top priority is high bandwidth, high speed, or a combination of features, you can use the PCI Compiler to meet your system requirements.
Altera’s PCI MegaCore functions are fully tested to meet the requirements of the PCI-SIG PCI Local Bus Specification, Revision 3.0 and Compliance Checklist, Revision 3.0. You can test drive Altera PCI MegaCore functions using the OpenCore Plus feature to compile, simulate, and hardware-test the functions within your custom logic. When you are ready to license a function, contact your local Altera sales representative.
The pci_mt32 and pci_t32 MegaCore functions provide fully compliant, 32-bit, 66-MHz PCI bus interface support, while the pci_mt64 and pci_t64 cores provide a fully compliant 64-bit, 66-MHz PCI bus interface. The pci_mt32, pci_t32, pci_mt64, and pci_t64 cores are optimized for the Stratix® FPGA series, Arria® GX FPGA series, Cyclone® FPGA series, and the HardCopy® ASICs series. Additionally, the pci_mt32 and pci_t32 cores are optimized for MAX® II CPLDs.
Figure 1. pci_mt32 Block Diagram
IP evaluation
Use the Altera OpenCore Plus Evaluation flow to test drive this IP core.
For more information on OpenCore Plus hardware evaluation using the PCI Compiler: 32-bit PCI master/target PCI, 32-bit PCI target, 64-bit PCI master/target, or 64-bit PCI target MegaCore functions, see AN 320: OpenCore Plus Evaluation of Megafunctions (PDF).
Technical support
Technical support for this PCI Compiler MegaCore function is provided by the Altera mySupport online issue tracking system. You may also search the Altera Knowledge Database or Altera Support Design Examples for topics or examples related to this function.
