32-Bit PCI Bus Master/Target Interface
Features
- Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
- Supports zero-wait state burst data transfer
- Provides bus initiator and target capability
- 33-MHz operating frequency
Block Diagram
Figure 1 shows the block diagram for the 32-Bit PCI Bus Master/Target Interface megafunction.
| Figure 1. Block Diagram |
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Description
The 32-bit PCI master/target interface megafunction is a flexible interface between a bus master device, such as a direct-memory access (DMA) controller or video coprocessor, and the PCI bus. The megafunction supports high bandwidth data transfer up to 133 Mbytes per second. All PCI configuration registers are included in the megafunction, and configuration requests are processed locally by the megafunction.
This megafunction also includes PCI target capability, which is useful for transferring data as a target and for setting up the control register of a bus mastering device.
The megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| EPF10K10 |
-3 |
650 |
0 |
33 MHz |
Contact Eureka Technology |
| EPF6016 |
-2 |
650 |
- |
33 MHz |
Contact Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, you can contact Eureka Technology, Inc. at: Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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