32-bit PCI Host Bridge
Features
- Fully supports PCI specification 2.1 and 2.2 protocols
- Designed for programmable logic device (PLD) and ASIC implementation in various system environments
- Fully static design with edge-triggered flip-flops
- Efficient back-end interface for different types of user devices
- Host bridge design includes bus master, bus target, and central system functions
- Generates standard PCI type 0 and type 1 configuration access
- Combines bus master and target functions
- Supports zero wait-state and user-inserted wait-state burst data transfer
- Dual write buffer supports write data posting
- User-controlled burst and non-burst data transfer
- Automatically handles configuration register read/write access
- Supports user-initiated target retry, disconnect, abort, and delayed transaction
- Includes all PCI-specific configuration registers
Block Diagram
Figure 1 shows the block diagram for the 32-bit PCI host bridge megafunction.
| Figure 1. Block Diagram |
 |
Description
The 32-bit PCI host bridge is designed for interfacing the host central processing unit (CPU) with the PCI bus. This core contains options to support a 32-bit or 64-bit back-end bus for different CPUs. The host bridge consists of three functions: bus master, bus target, and configuration access generation.
A highly efficient and flexible back-end bus interfaces with the system CPU and user-defined logic such as direct memory access (DMA) and memory controllers. The core utilizes the double data buffer design approach that minimizes design gate count and achieves the highest possible data bandwidth at the same time.
The host bridge core allows the CPU or user logic to initialize the entire system during power-up reset. Configuration Mechanism 1, as defined by the PCI specification, is implemented by the host bridge and supports both type zero and type one transactions.
This megafunction is available in Altera hardware description language (AHDL), Verilog, VHDL, and netlist format. Megafunction sizes vary with features and customization. Eureka Technology can customize the design according to specific user requirements. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for
the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX
APEX
ACEX |
|
1,400 |
0 |
33 MHz |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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