from Eureka Technology Inc.
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Features
- Fully compliant with peripheral component interconnect (PCI) special interest group (SIG) PCI Local Bus Specification, Revision 2.2
- 64-bit PCI bus
- Zero-wait state burst data transfer with internal write buffer
- 33-MHz operating frequency
Block Diagram
Figure 1 shows the block diagram for the 64-Bit PCI Bus Target Interface megafunction.
| Figure 1. Block Diagram |
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Description
The 64-bit PCI target megafunction is designed for interfacing user logic with a 64-bit PCI bus. This megafunction is a very compact design that minimizes logic cell count while offering double the bandwidth performance of a 64-bit bus system.
An internal write buffer is included in this design to support zero-wait state burst transfer and a very long burst length. The megafunction can transfer data up to 266 Mbytes per second. Both 64-bit and 32-bit data transfer rates are supported by this megafunction. All compliant configuration registers are included in the megafunction and all configuration accesses are processed automatically.
The megafunction is available in Altera Hardware Description Language (AHDL), Verilog HDL, VHDL, and netlist format. Megafunction sizes vary with features and customization. Contact Eureka Technology for a logic cell count that is based on user specifications.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | |||||
| Device | Speed Grade | Utilization | Performance (fMAX) |
Parameter Setting | |
|---|---|---|---|---|---|
| Logic Cells | EABs (1) | ||||
| EPF10K30 | -2 | 500 | 0 | 33 MHz | Contact Eureka Technology |
| EPF6016 | -2 | 500 | - | 33 MHz | Contact Eureka Technology |
Note:
Contact Information
For additional information, you can contact Eureka Technology, Inc. at:
Eureka Technology, Inc.4962 El Camino Real
Suite 108
Los Altos, CA 94022
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
