from PLDA
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Features
- Compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2
- Compliant with the Personal Computer Memory Card International (PCMCIA) CardBus PC Card Standard, Release 8
- Supports Power Management Specification, Revision 1.1 for all power states
- Supports CIS register and CIS tupple space
- Supports function event registers
- Supports clock management (CLKRUN#)
- Compliant with the PICMG CompactPCI Specification, Revision 2.1
- Compliant with the PICMG Hot Swap Specification, Revision 1.0
- Compliant with the PCI SIG PCI Local Bus Mini PCI Specification, Revision 1.0
- Additional standards supported include PMC (MMSC PMC Specification, Draft 2.4) and PC104+ (PC/104 PC/104+ Specification, Revision 1.0)
- Optimized for Altera® FLEX® 10KE, ACEX™ 1K, APEX™ 20K, APEX 20KE, APEX 20KC, APEX II, and ARM®- and MIPS-based™ Excalibur™ devices
- 66-MHz PCI-compliant with FLEX 10KE, ACEX 1K, APEX 20KE, and Excalibur devices in -1 speed grade, and with all APEX II devices
- Operating frequency of over 100 MHz on specific Altera devices for utilization in embedded systems
- VHDL-RTL source code available (with application-specific integrated circuit (ASIC) licenses only)
- Silicon-proven core with over 300 licensees worldwide, including ASIC licensees
- Risk-free OpenCore® evaluation available
- Target-mode advanced features include:
- True multifunction support for up to 4 functions, with up to 4 interrupt lines
- Supports all base address registers (BARs) in both 32-bit and 64-bit addressing modes
- Embedded memory controller for each implemented BAR allows for direct memory interfacing (SRAM, DPRAM, and first-in first-out (FIFO))
- Configuration space can be mapped into memory space
- For additional features, refer to the PCI MegaCore Function User Guide
- Master-mode advanced features include:
- Up to four embedded direct memory access (DMA) channels, independently operated
- Complete support of memory write and invalidate (MWI) command for DMA-transfer optimization
- 64-bit addressing and 64-bit data transfers supported and dynamically negotiated
- For additional features, refer to the PCI MegaCore Function User Guide
- Ready for PCI host-bridge implementations when used in conjunction with PLD Applications' PCI arbiter core
Block Diagram
Figure 1 shows the block diagram for the 32/64-bit PCI bus master/target interface megafunction.
| Figure 1. Block Diagram |
 |
Description
The PCI interface function is fully parameterizable and you can use it in any application that requires interfacing to communications buses based on the PCI protocol, such as regular PCI, CompactPCI (hot swap), CardBus, Mini PCI, PC104+, and PMC.
This function handles all required features for the bus standard it supports and provides some unique features such as multi-function, multi-DMA, and embedded memory controllers. As a parameterized function, you can enable or disable most of the core capabilities depending on design requirements, thus optimizing silicon utilization and performance. You can operate this function at over 100 MHz on specific devices. Additionally, it supports full-speed, zero wait-states burst transfers in both slave and master operation.
The PCI function's backend interface is designed to allow easy integration of a wide range of peripherals such as processors, digital signal processors, telecom functions, and memories.
This function also implements all the necessary features for a utilization in host bridging applications (e.g., self-configuration, access to configuration status register, ability to generate configuration accesses, PCI arbiter).
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction | ||||
| Device | Speed Grade | Utilization | Performance (2) |
|
|---|---|---|---|---|
| Logic Cells | EABs/ESBs (1) | |||
| EP1K50 | -1 | 1,700 (3) | 0 | 110 MHz |
| EPF10K130E | -1 | 1,700 (3) | 0 | 75 MHz |
| EP20K400E | -1 | 1,700 (3) | 0 | 75 MHz |
| EP20K1000C | 7 | 1,700 (3) | 0 | 80 MHz |
| EP2A40 | 7 | 1,700 (3) | 0 | - |
- EAB = Embbeded array blocks; ESB = Embedded system blocks
- Typical 64-bit master/target core implementation with 2 DMA channels, 3 BARs, and a single function
- The figures given are for a 64-bit reference design.
Deliverables
In addition to the synthesis libraries, the megafunction ships with a complete simulation environment, including a powerful VHDL testbench and functional simulation libraries for most popular simulators.
Additional deliverables are also included in the package and comprise:
- Various wizards for customizing the function, creating constraints files, or creating testbench templates
- Software kit with PCI C API and GUI applications for monitoring and exercising PCI agents
- Reference designs demonstrating DMA operation, slave accesses, and CardBus features
Development PCI boards and bus analyzers are also available, including 64-bit/66MHz PCI with SDRAM, SRAM, FLASH, Digital I/O pins, LVDS inputs/outputs, and PMC daughter card extensions. See the PLD Applications web site for more information.
Contact Information
For additional information, contact PLD Applications at:
PLD Applications
Europarc Pichaury A2
1330, rue Guillibert
13856 Aix-en-Provence Cedex 3, France
Tel. USA: 1-866-513-0362 (toll free)
Tel. Intl: +33-(0)-442-393-600
Fax. Intl: +33-(0)-442-394-902
E-mail: email@plda.com
URL: http://www.plda.com
