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主页 > 产品 > IP > 接口与外设 > 外设 > CZ80CTC Programmable Counter-Timer 打印此页 订阅电邮新闻 CZ80CTC Programmable Counter-Timer from CAST, Inc. The CZ80CTC four-channel counter/timer circuit (CTC) megafunction can be programmed by system software for a broad range of counting and timing applications. The four independently programmable channels of the CZ80CTC satisfy common microcomputer system requirements for event counting, interrupt and interval timing, and clock rate generation. System design is simplified because the CTC connects directly to the CZ80SIO with no additional logic. In larger systems, address decoders and buffers may be required. Features Control unit with 8-bit instruction decoder Four independently programmable counter/timer channels, each with: Readable downcounters Downcounters that reload automatically at zero count Selectable prescalers which divide system clock frequency by a factor of 16 or 256 Selectable positive or negative trigger initiates timer operation Interfaces directly to the CPU, or to the CZ80SIO for baud rate generation Standard Z80 family daisy-chain interrupt structure provides fully vectored prioritized interrupts without external logic (CTC may used as an interrupt controller). Synchronous design without internal tri-states and a synchronous reset Block Diagram Figure 1. The Block Diagram for the CZ80CTC Megafunction Device Utilization & Performance Table 1 lists the typical device utilization results for the megafunction. Table 1. CZ80CTC Megafunction Device Utilization Target Device Speed Grade Utilization Performance (fMAX) LEs(1) Memory Stratix® II 2S15 -3 509 - 315 MHz Stratix 1S10 -5 523 - 182 MHz Cyclone® 1C3 -6 559 - 169 MHz ACEX® 1K30 -1 600 - 113 MHz APEX™ II 2A15 -7 702 - 154 MHz APEX 20KE30 -1 649 - 109 MHz Notes: LE = logic elements; the LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by the Quartus® II software. Deliverables Encrypted Licenses Post-synthesis Altera® hardware description language (AHDL) or EDIF Assignment & configuration Symbol file Include file Vectors for testing the functionality of the megafunction HDL Source Licenses VHDL or Verilog register transfer level (RTL) source code Testbench Vectors for testbench Expected results for testbench Simulation script Synthesis script Contact Information For additional information, contact CAST, Inc. at: CAST, Inc. 11 Stonewall Court Woodcliff Lake, NJ 07677, USA Tel: +1 (845) 353-6160 Fax: +1 (845) 727-7607 E-mail: OpenCore@cast-inc.com URL: www.cast-inc.com   给本页评分

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