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H16550

from CAST, Inc.

View Literature
Request Free Evaluation



AMPP Approved
OpenCore Support



Features

  • Capable of running all existing 16450 and 16550a software
  • In first-in first-out (FIFO) mode, the transmitter and receiver are each buffered with 16-byte FIFO buffers to reduce the number of interrupts presented to the CPU
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Independently controlled transmit, receive, line status, and data set interrupts
  • Programmable baud generator divides any input clock by 1 (216- 1) and generates the 16x clock
  • Independent receiver clock input
  • Modem control functions (CTS, RTS, DSR, DTR, RI, and DCD)
  • Fully programmable serial interface
  • False start bit detection
  • Complete status register
  • Internal diagnostic capabilities: loopback controls for communications link fault isolation
  • Full prioritized interrupt system controls

Block Diagram

Figure 1 shows a block diagram of the function.

Figure 1: Block Diagram

Figure 1. Block diagram for H16550 core

Description

The H16550 is a standard universal asynchronous receiver/transmitter (UART) providing 100% software compatibility with the popular Texas Instruments 16550 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.

The H16550 can be run in either 16450-compatible character mode or in 16550-compatible FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead. Developed for easy reuse in Altera® FPGA applications, the H16550 is available with several device families and optimized with competitive utilization and performance characteristics.

Device Utilization & Performance

Table 1 lists the typical device utilization results for the megafunction.

Table 1. Typical Device Utilization for the Megafunction
Target Device Speed Grade Utilization Performance
(fmax)
Logic Elements (LEs) Embedded array blocks (EABs) I/O Pins
EPF10K30E -1 749 3 40 69 MHz
EP20K30E -1 648 3 40 80 MHz
EP1K30 -1 749 3 40 69 MHz

Deliverables

  • EDIF netlist
  • Assignment & configuration
  • Symbol file
  • Include file
  • Vectors for testing the functionality of the megafunction including expected results
  • Documentation

Contact Information

For additional information, contact CAST. Inc. at:

CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: OpenCore@cast-inc.com
WWW: http://www.cast-inc.com

 

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