H16750 UART
Features
- Capable of running all existing 16450 & 16550 software
- In first-in first-out (FIFO) mode, transmitter & receiver are each buffered with up to 256-bytes FIFOs to reduce the number of interrupts presented to the CPU
- Available with FIFO sizes of 8-, 16-, 32-, 64-, 128- or 256-bytes
- Adds or strips standard asynchronous communication bits (start, stop & parity) to or from the serial data
- Independently controlled transmit, receive, line status & data set interrupts
- Programmable baud generator divides any input clock by 1 to (216 - 1) and generates the 16x clock
- Independent receiver clock input
- Modem control functions (CTSn, RTSn, DSRn, DTRn, RIn & DCDn)
- Programmable Auto-CTSn & Auto-RTSn
- In Auto-CTSn mode, CTSn controls the transmitter
- In Auto-RTSn mode, the receiver FIFO contents & threshold control RTSn
- Serial port has an optional Infrared Data Association (IrDA) data port
- Fully programmable serial interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even-, odd-, or no-parity bit generation & detection
- 1-, 1½-, or 2-stop bit generation
- Baud generation
- False start-bit detection
- Complete status register
- Internal diagnostic capabilities, including loop-back controls for communications link fault isolation
- Fully-prioritized interrupt system controls
Description
The H16750 is a standard UART providing 100 percent software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel conversion on data originating from modems or other serial devices, and performs parallel-to-serial conversion on data from a CPU to these devices.
The H16750 can be run in either 16450-compatible character mode or FIFO mode, where an internal FIFO relieves the CPU of excessive software overhead.
Developed for easy reuse in ASIC and FPGA applications, the H16750 is available optimized for several technologies with competitive utilization and performance characteristics.
Block Diagram
Figure 1 shows a block diagram of the function.
Figure 1. Block Diagram
Device Utilization & Performance
Table 1 lists the typical device utilization results for the megafunction.
|
Table 1. Typical Device Utilization for the Megafunction |
|
Target Device |
Speed Grade |
Utilization |
Performance
(fmax) |
Parameter Setting
|
|
Logic Elements (LEs) (1) |
Memory |
|
Cyclone™ EP1C20 |
-6 |
617 |
2 M4K |
116 MHz |
No IrDA |
|
Stratix® EP1S20 |
-5 |
617 |
2 M4K |
126 MHz |
No IrDA |
| Stratix II EP2S60 |
-3 |
525 |
2 M4K |
175 MHz |
No IrDA |
|
Cyclone EP1C20 |
-6 |
631 |
2 M4K |
114 MHz |
IrDA |
|
Stratix EP1S20 |
-5 |
631 |
2 M4K |
123 MHz |
IrDA |
|
Stratix II EP2S60 |
-6 |
546 |
2 M4K |
180 MHz |
IrDA |
Note to Table 1:
-
The LE count for Stratix II devices is based on the number of adaptive look-up tables (ALUTs) used for the design as reported by Quartus® II software.
Deliverables
- EDIF netlist
- Assignment & configuration
- Symbol file
- Include file
- Vectors for testing the functionality of the megafunction, including expected results
- Documentation
Contact Information
For additional information, contact CAST, Inc. at:
CAST, Inc.
11 Stonewall Court
Woodcliff Lake, NJ 07677
USA
Phone: +1 (845) 353-6160
Fax: +1 (845) 727-7607
E-mail: info@cast-inc.com
URL: www.cast-inc.com
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