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主页 > 产品 > IP > 接口与外设 > 外设 > DSPI - Serial Peripheral Interface Master/Slave 打印此页 订阅电邮新闻 DSPI - Serial Peripheral Interface Master/Slave from Digital Core Design Features Serial peripheral interface (SPI) Master Master and multi-Master operation System error detection Mode fault error Write collision error Interrupt generation Supports speeds up to 1/4 of system clock 8 Slave select lines Bit rates generated 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, and 1/512 of system clock Four transfer formats supported Simple interface allows easy connection to microcontrollers SPI Slave Slave operation System error detection Interrupt generation Supports speeds up 1/4 of system clock Simple interface allows easy connection to microcontrollers Four transfer formats supported Fully synthesizable, static synchronous design with no internal tri-states Technology independent hardware description language (HDL) source code Block Diagram Figure 1 shows a block diagram of the function. Figure 1. DSPI — Serial Peripheral Interface Master/Slave View full detail (76 KB) Description The DSPI core is a fully configurable SPI Master/Slave devicethat allows user to configure polarity and phase of serial clock signal SCK. The DSPI allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. DSPI data is simultaneously transmitted and received. The DSPI core is a technology-independent design that can be implemented in a variety of process technologies. The DSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a Master or a Slave device. Data rates are as high as 1/4 of the clock rate. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a Master, software selects one of four different bit rates for the serial clock. The DSPI core automatically drives-controlled by the slave select control register (SSCR)-slave select outputs (SS7O-SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master modefault detector automatically disables DSPI output drivers if more than one SPI device simultaneously attempts to become bus master. Device Utilization Example Table 1 lists the typical device utilization results for the megafunction. Table 1. Typical Device Utilization Device Speed Grade Utilization Performance (fMAX) Parameter Setting LEs EABs Stratix® -6 164 0 273 MHz Contact DCD APEX™ 20KE -1 180 0 171 MHz Contact DCD APEX 20KC -7 180 0 207 MHz Contact DCD APEX II -7 179 0 247 MHz Contact DCD Deliverables HDL source code package includes: VHDL or Verilog source code VHDL or Verilog test bench environment Active-HDL automatic simulation macros ModelSim® automatic simulation macros Full tests with reference responses Synthesis scripts Encrypted megafunction package includes: EDIF or Text Design File (.tdf) netlist optimized for particular technology Core instantiation inside Quartus® II or MAX+PLUS® II environments Symbol, include, assigments, and configuration files Compilation, simulation, and programming ready project Each package includes: Technical documentation Installation notes HDL core specification Data sheet Example application Technical support Intellectual property (IP) core implementation support Three months of maintenance, including phone and e-mail support Contact Information For additional information, contact Digital Core Design at: Wroclawska 94 41-902 Bytom Poland Tel: +48 32 2828266 Fax: +48 32 2827437 E-mail: info@dcd.pl http://www.digitalcoredesign.com 给本页评分

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