AHB Slave
Features
- Supports the advanced high-performance bus (AHB) bus interface to the ARM® CPU
- User interface designed for high-speed access to two sets of on-chip or off-chip modules
- Four write buffers to process posted write
- Dual read buffers to process CPU read
- Read access to external bus handled as a delay read to avoid system deadlock
- Supports burst transfer and zero wait state to maximize data bandwidth
- Supports data width of 8, 16, and 32 bits
- Supports burst transfers up to 16 words of data
- Supports early burst termination and CPU master busy
- Multiple bus slave is supported by Ready signal inputs and outputs
- Programmable address mapping to multiple address spaces
- User interface optimized to access a secondary bus, such as peripheral component interconnect (PCI) and memory subsystems based on SDRAM and flash
- Optimized for ASIC and programmable logic device (PLD) implementations, including ExcaliburTM PLDs
Block Diagram
Figure 1 shows a block diagram for the megafunction.
| Figure 1. Block Diagram |
 |
Description
The EP140 is an AHB slave megafunction designed to interface user logic with the ARM® CPU. It decodes the AHB address and dispatches the request to the user logic through two user interface ports. The bus slave also regulates the data flow between all ports to optimize performance. Different user logic implementations such as a SDRAM controller, flash controller, PCI host bridge, direct memory access (DMA), or universal asynchronous receiver/transmitter (UART), can be connected to the AHB through the slave.
The EP140 is capable of simultaneously transferring data between the AHB and the two user interfaces. The B port user interface is optimized for peripheral bus controller access such as PCI bus access, and the M port user interface is optimized for memory controller access. However, both user interface ports use a very simple, user-friendly protocol so that different types of user logic other than PCI and a memory controller can be connected to either interface port.
The AHB slave contains four write buffers, two for each user interface. Each write buffer can store up to 64 bytes of data. The dual-write buffer structure allows the CPU to post write data into one buffer while the user interface is extracting data from the other write buffer. The CPU can post up to four different write commands can be posted into the AHB slave while the user logic processes the write request.
The slave can handle reading by the AHB as a delay read or as a real-time read. The delay read method is suitable for interfacing with an external bus such as a PCI bus. With this method, the AHB slave retries the CPU while it is reading data from the user logic. Instead of inserting a wait state while waiting for the return data, the AHB slave uses a retry to free up the AHB for other accesses. Once the read data is available, the data is returned to the CPU with a zero wait state in the subsequent read. The primary benefit of the delay read method is to prevent deadlock between the external bus and the AHB.
The real-time read method is suitable for reading a device that has a small read latency, such as an SDRAM or other memory controller. The bus slave inserts a wait state on the AHB while waiting for data to return from the memory. No retry is issued, so that data is returned to the CPU as soon as it arrives from memory.
The AHB slave contains two user interfaces. Each interface contains its own set of write buffers to avoid sharing the write buffers and read buffers and to avoid resource dependence. The buffers also support CPU access using different data sizes from the user logic. The AHB slave supports data sizes of 8, 16 and 32 bits from the CPU while the user logic transfers data at a 32-bit rate.
The AHB Slave megafunction is available in AHDL, Verilog, and VHDL, as well as netlist format. Megafunction sizes vary with features and customization. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Modifiable Parameters
Eureka Technology can customize the design according to specific user requirements. Contact Eureka Technology or visit their web site for more information.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX®
APEXTM
ACEXTM |
|
800 |
0 |
75 MHz |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
USA
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
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