AHB to PCI Host Bridge
Features
- Fully supports the PCI specification versions 2.1 and 2.2
- Supports the advanced high-performance bus (AHB) protocol
- Downstream access transfer from the AHB to the PCI bus
- Upstream access transfer from the PCI bus to the AHB
- AHB and PCI bus operate at independent clock domains
- Total of six write buffers for write data posting for all interfaces
- Read access to the PCI bus handled as a delay read to prevent system deadlock
- Supports AHB burst transfers up to 16 words of data
- Supports all AHB slave response types when functioning as AHB master
- PCI interface includes bus master, bus target, and configuration access initiation
- Generates standard PCI type 0 and type 1 configuration accesses
- Supports early burst termination and CPU master busy
- Automatic handling of configuration register read/write access
- Supports target retry, disconnect, abort, and wait-state insertion
- Parity generation and parity error detection
- Includes all PCI-specific configuration registers
- Supports high-speed bus request and bus parking
- Optional PCI bus arbiter with fix, rotating, and custom priority
- Optimized for ASIC and programmable logic device (PLD) implementations, including ExcaliburTM PLDs
Block Diagram
Figure 1 shows a block diagram for the megafunction.
| Figure 1. Block Diagram |
 |
Description
The EP454 PCI host bridge megafunction is designed to interface the ARM® CPU with the PCI bus and to handle forward data access from both the upstream and downstream directions. The host bridge consists of three functional units: the AHB slave, AHB master, and PCI interface. The AHB and the PCI bus can operate at two different clock domains.
Any bus mastering devices on the AHB can also access the host bridge. The core has multiple data buffers to achieve high-speed data posting, prevent bus deadlock, and allow clock domain crossing for the data.
The host bridge function allows the CPU to initialize the entire system during power-up reset using the standard PCI protocol. Both type zero and type one transactions are supported. The CPU requests configuration access on the PCI bus by writing to or reading from the CONFIG_ADDR and CONFIG_DATA registers, which are contained in the host bridge.
Upon AHB requests, the host bridge initiates memory or I/O read and write on the PCI bus. It contains four write buffers, two in the AHB clock domain and two in the PCI clock domain, to post write data. Data can be written from the AHB at the same time as a write operation is running on the PCI bus.
Reading by the AHB is handled as a delay read. The AHB slave retries the CPU while it is reading data from the PCI bus. Instead of inserting a wait state while waiting for the return data, the AHB slave uses an AHB retry to free up the AHB for other accesses. Once the read data is read from the PCI bus, the data returned to the CPU with a zero wait state in the subsequent read. The main benefit of the delay read method is to prevent deadlock between the PCI bus and the AHB.
The host bridge functions as a PCI target when accessed by an external PCI bus master. The PCI target contains two write buffers and a read buffer to handle write posting and transfer data across the two clock domains. The request received from the PCI bus is forwarded upstream to the AHB through the built-in AHB master. When functioning as an AHB master, the host bridge supports all bus slave response types, wait state insertions, and burst data transfer.
The megafunction is available in AHDL, Verilog, and VHDL, as well as netlist format. Megafunction sizes vary with features and customization. Please contact Eureka Technology or visit the Eureka Technology web site for a complete data sheet.
Modifiable Parameters
Eureka Technology can customize the design according to specific user requirements. Contact Eureka Technology or visit their web site for more information.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for
the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
FLEX®
APEXTM
ACEXTM |
|
4800 |
0 |
75/33 MHz |
Contact
Eureka Technology |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Eureka Technology, Inc. at:
Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
USA
Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com
|
文档资料
> 
