AHB to SDRAM Controller

from Eureka Technology Inc.

Features

SDRAM controller interfaces directly with advanced high-performance bus (AHB) and user interface
Built-in arbitration between two access ports
Second access port allows memory sharing with user logic devices
Dual write buffer for simultaneous write posting and SDRAM access
Dedicated read buffer with data width matching
Supports early burst termination and CPU master busy on the AHB
Supports AHB data width of 8, 16, and 32 bits
Zero-wait-state burst data transfer on both the AHB interface and SDRAM
Operates on both discrete SDRAM chips and PC100/133 SDRAM DIMM
Supports industry-standard SDRAM from 64-Mbit to 256-Mbit device sizes
Pipeline access allows continuous data transfer without a wasted cycle
Fast page access on row address matching
Independent row address matching for each of the four SDRAM banks
Programmable memory size: 4, 8, 16, and 32 bits per SDRAM
Programmable SDRAM access timing parameters
Automatic refresh generation with programmable refresh intervals
Optimized for ASIC and programmable logic device (PLD) implementations, including Excalibur^™ PLDs

Block Diagram

Figure 1 shows a block diagram for the megafunction.

Figure 1. Block Diagram

Description

The SDRAM controller is a high-performance SDRAM controller designed for transferring data to and from any industry-standard SDRAM or PC100/133 SDRAM DIMM at the highest possible data rate.

The EP 504 AHB SDRAM controller provides high-speed SDRAM for the system. It features two access ports. One port interfaces directly to the AHB, and the other access port is optimized for system core logic such as direct memory access (DMA) or a PCI bus bridge. The SDRAM controller megafunction contains a built-in arbitration unit to allow both the AHB CPU and system core logic to share SDRAM access. A rotating priority scheme ensures equal sharing of the memory bandwidth.

The pipeline feature of the SDRAM controller allows the user port to specify the next access address while the current data transfer is in progress. Multiple data transfers can be cascaded together to read or write data from the SDRAM continuously, without any wasted cycle between accesses.

Another performance enhancement of the SDRAM controller is that it uses fast page access if there is a row hit. For each of the four internal banks, the SDRAM controller keeps the previous accessed row open. If the new request hits the same row, a column access is performed, eliminating row access time. The SDRAM controller simultaneously keeps track of four open rows, one for each bank.

The SDRAM controller can be programmed to support different sizes and configurations of SDRAMs. The SDRAM device sizes supported are 64 Mbits, 128 Mbits, and 256 Mbits. The data width per SDRAM device can be programmed to 4, 8, 16 or 32 bits. The user can also use multiple SDRAMs to build an wider memory subsystems.

The SDRAM controller is fully programmable. All access timing parameters such as column access (CAS) latency, row-to-column delay, and refresh interval are programmable to support different speed grades of SDRAM devices and different operating frequencies. All the timing parameters can be modified during run-time by a separate access port. The timing parameters can also be set to the proper default values during compile time so that there is no need to program them during run-time.

The user interface of the SDRAM controller is a user-friendly synchronous bus, similar to the I960 microprocessor interface. The user provides the address for each access and the SDRAM controller automatically generate the row (RAS) and column (CAS) access cycles to transfer data. The user can specify a single or burst data transfer. In a burst data transfer, zero wait state data bursting is supported to maximize memory bandwidth. Periodically, the SDRAM controller issues an SDRAM refresh cycle, which is transparent to the AHB and the user interface.

This megafunction is available in Altera^® hardware description language (AHDL), Verilog, and VHDL as well as netlist format. Megafunction sizes vary with features and customization. Please contact Eureka Technology or visit Eureka Technology web site for a complete data sheet.

Modifiable Parameters

Eureka Technology can customize the design according to specific user requirements. Contact Eureka Technology or visit their web site for more information.

Device Utilization Example

Table 1 lists the typical device utilization results for the megafunction.

*Table 1. Typical Device Utilization for the Megafunction*
Device	Speed Grade	Utilization		Performance (f_MAX)	Parameter Setting
		Logic Cells	EABs (1)
FLEX^® APEX^TM ACEX^TM		1600	0	75 MHz	Contact Eureka Technology

Note:

EABs = Embedded array blocks

Contact Information

For additional information, contact Eureka Technology, Inc. at:

Eureka Technology, Inc.
4962 El Camino Real
Suite 108
Los Altos, CA 94022
USA

Tel. (650) 960-3800
Fax (650) 960-3805
E-mail: info@eurekatech.com
WWW: http://www.eurekatech.com

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