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主页 > 产品 > IP > 接口与外设 > RapidIO > RapidIO MegaCore Function 打印此页 订阅电邮新闻 RapidIO MegaCore Function from Altera Corporation The Serial RapidIO® (SRIO) standard has been adopted by a significant portion of the wireless industry as a high-speed interconnect and is typically used between digital signal processors and between the control plane processors and memory. SRIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical medium attachment (PMA)—such as XAUI for the 3.125-Gbps data rate. Features Robust solution End-point intellectual property (IP) core, testbenches with proven interoperability with leading digital signal processor and switch vendors Compliant to RapidIO specification, Revision 1.3 Flexible 1.25, 2.5, 3.125-Gbps lane rates -x1, x4 link widths Physical layer based on embedded transceivers or with parallel XGMII interface to external transceivers Modular layered SRIO architecture Physical, transport, and logical layer separations Easy configuration provides ways to reduce resource utilization to create smaller MegaCore® variations depending on application needs Ease of use MegaWizard® GUI allows easy manualoptimization of parameters such as interface FIFO depths, address translation windows, and output differential voltage and pre-emphasis SOPC Builder support  For a system-level integration-ready solution, you can save several man-months of design time by selecting all RapidIO layers—including features such as address translation and simple Avalon®-Memory-Mapped (MM) and Avalon-Streaming (ST) FIFO interfaces. Figure 1 shows an example of a system built using SOPC Builder with Nios® II soft embedded processor as a processing element. The program memory can include“boot code” for system-level enumeration of the various end points and also configure the capability address registers of the endpoints and the MegaCore function. Figure 1. A Complete SRIO System OpenCore Plus Evaluation Use the Altera®OpenCore Plus evaluation flow to test drive this IP core. Performance Typical expected performance and utilization figures for this core are provided in theRapidIO MegaCore Function User Guide (PDF). Technical Support For technical support on this MegaCore function, visit theAltera mySupport online issue tracking system. You may also search for related topics on this function in theAltera KnowledgeDatabase. A web-based technical training on configuring the SRIO MegaCore function is also available. Related Documents RapidIO MegaCore Function User Guide (PDF) MegaCore IP Library Release Notes and Errata(PDF) 给本页评分

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