SerialLite II MegaCore Function
from Altera Corporation
Features
- Physical layer features
- 622 Mbps to 6.375 Gbps per lane
- Single or multiple lane support (up to 16 lanes)
- 8-bit, 16-bit, or 32-bit data path per lane
- Symmetric, asymmetric, unidirectional/simplex or broadcast mode
- Optional payload and idle scrambling
- Self-synchronizing link state machine
- Channel bonding scalable up to 16 lanes
- Synchronous or asynchronous operation
- Automatic clock rate compensation for asynchronous use
- +/-100 and +/-300 parts per million (ppm)
- Link layer features
- Atlantic™ interface compliant
- Support for two types of user packets: data packet and priority packet
- Optional packet integrity protection using cyclic redundancy code (CRC-32 or CRC-16)
- Optional retry-on-error for priority packets
- Individual port (data/priority) flow control
- Unrestricted data and priority packet size
- Optional link management packets
- Full support of asymmetrical, unidirectional, and broadcast modes at rates up to 3.125 Gbps in Stratix® GX devices and at up to 6.375 Gbps in Stratix II GX devices
- Includes the scramble/descramble modes
- Easy-to-use MegaWizard® interface
- Intellectual property (IP) functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators
- Support for OpenCore Plus evaluation
General Description
The SerialLite II MegaCore® function provides a simple and lightweight way to move data from one point to another reliably, at high speeds. It consists of a serial link of up to 16 bonded lanes, with logic to provide a number of basic and optional link support functions. The Atlantic interface is used as the primary access for delivering and receiving data.
The SerialLite II protocol specifies a link that is simple to build, uses as little logic as possible, and requires little work to implement. The SerialLite II MegaCore function uses all of the features available in the SerialLite II protocol, and you can parameterize it through a powerful MegaWizard interface.
A link built using the SerialLite II MegaCore function can operate from 622 Mbps to 6.375 Gbps per lane. Link reliability is enhanced by the 8B/10B encoding scheme and optional cyclical redundancy check (CRC) capabilities. Further reductions in the bit-error rate can be achieved using the optional retry-on-error feature. Data rate and consumption mismatches can be accommodated using the optional flow-control feature to ensure that no data is lost.
OpenCore Plus Evaluation
Use the Altera® OpenCore Plus Evaluation flow to test drive this IP core.
Performance
Typical expected performance and utilization figures for this core are provided in the SerialLite II User Guide (PDF).
Technical Support
For technical support on this MegaCore function, please visit the Altera mySupport online issue tracking system. You may also search for related topics on this function in the Altera Knowledge Database.
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