MUSBFSFCD1 USB 1.1 Full Speed Function Controller
Features
- Designed to comply with USB standard for full-speed (12-Mbps) functions
- Netlist configuration (three end points):
- Bulk IN, double buffered 64-byte FIFO buffer
- Bulk OUT, double buffered 64-byte FIFO buffer
- Interrupt IN, double buffered 64-byte FIFO buffer
- Original RTL version of core is configurable for up to 15 additional IN or OUT end points with configurable end point direction and FIFO buffers for each end point
- 8-bit synchronous PVCI-compatible CPU interface (Virtual Component Interface, as defined by VSIA; OCB 2 version 1.0)
- Support for DMA access to FIFO buffers
- Synchronous RAM interface for FIFO buffers
- Supports Suspend and Resume signaling
- Optimized for use with Altera® Nios® embedded processor
Block Diagram
Figure 1 shows the block diagram for the Mentor Graphics MUSBFSFCD1 USB 1.1 Full Speed Function Controller.
| Figure 1. Block Diagram |
 |
Description
The MUSBFSFCD1 USB 1.1 Full Speed Function Controller from Mentor Graphics is an implementation of the Mentor MUSBFSFC soft core as a netlist for Altera programmable logic devices (PLD). The MUSBFSFC core provides a USB function controller that is designed to comply with the USB 1.1 and 2.0 specifications for full-speed (12-Mbps) functions. The core configuration used to generate this netlist has three end points:
-
Bulk IN, double buffered 64-byte FIFO
-
Bulk OUT, double buffered 64-byte FIFO
-
Interrupt IN, double buffered 64-byte FIFO
The original register transfer level (RTL) version of the core is user-configurable for up to 15 IN end points and for up to 15 OUT end points in addition to End point 0. These additional end points can be individually programmed for bulk/interrupt or isochronous transfers. Each end point requires a FIFO buffer to be associated with it. The MUSBFSFC has a RAM interface for connecting to a single block of synchronous single-port RAM which is used for all the end point FIFO buffers (added by the user). The MUSBFSFC function's RAM interface is configurable for an end point 0 FIFO that is 8, 16, 32 or 64 bytes deep. Other end point FIFO buffers may be from 8 to 2,048 bytes deep and can buffer either one or two packets. Separate FIFO buffers may be associated with each end point: alternatively an IN end point and the OUT end point with the same end point number can be configured to use the same FIFO buffer, for example to reduce the size of RAM block needed.
Access to the FIFO buffers and the internal control/status registers is via an 8-bit PVCI-compatible synchronous CPU interface (as defined by VSIA) and there is support for DMA access to the end point FIFO buffers. The MUSBFSFCD1 function provides all of the USB packet encoding, decoding, and checking, interrupting the CPU only when end point data has been successfully transferred.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| APEX™ 20KC |
-1 |
2650 |
0 |
90.79 MHz |
Netlist is a fixed configuration of a configurable core. |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Mentor Graphics at:
Mentor Graphics
1001 Ridder Park Dr.
San Jose, CA 95131
Tel. (408) 487-7039
Fax (408) 487-7380
Email: mentor_ip@mentor.com (Netlist Sales)
URL: www.mentor.com/products/ip/index.cfm
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