MUSBHSFCD1 USB 2.0 High-Speed Function Controller
Features
- Designed to USB standard for high-/full-speed (480-/12-Mbps) functions
- Netlist configuration:
- 3 IN end points (including control endpoint)
- End point 1 = 1,024 bytes, end point 2 = 512 bytes
- 3 OUT end points (including control endpoint)
- End point 1 = 1,024 bytes, end point 2 = 512 bytes
- UTMI transceiver macrocell interface data width = 16 bits
- Original register transfer level (RTL) version of core is configurable for up to 16 IN or OUT end points (0 to 15) with configurable end point direction and FIFO buffer sizes (8 to 8,192) for each end point
- 16-/32-bit synchronous BVCI-compatible CPU interface (virtual component interface, as defined by VSIA; OCB 2 version 1.0)
- Support for DMA access to FIFO buffers
- Synchronous RAM interface for FIFO buffers
- Supports Suspend and Resume signaling
- Optimized for use with Altera® Nios® embedded processor
Block Diagram
Figure 1 shows the block diagram for the Mentor Graphics MUSBFSFCD1 USB 2.0 High-Speed Function Controller.
| Figure 1. Block Diagram |
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Description
The MUSBHSFCD1 USB 2.0 High-Speed Function Controller from Mentor Graphics is an implementation of the Mentor MUSBHSFC soft core as a netlist for Altera programmable logic devices (PLD). The MUSBHSFC core provides a USB function controller that was designed to the USB 2.0 specification for high-/full-speed (480-/12-Mbps) functions. The core configuration used to generate this MUSBHSFCD1 netlist is:
- 3 IN end points (including control end point): end point 1 = 1,024 bytes, end point 2 = 512 bytes
- 3 OUT end points (including control end point): end point 1 = 1,024 bytes, end point 2 = 512 bytes
- UTMI transceiver macrocell interface data width = 16 bits
The original register transfer level (RTL) version of the core is user-configurable for up to 15 IN end points and up to 15 OUT end points in addition to end point 0. These additional end points can be individually programmed for bulk/interrupt or isochronous transfers. Each end point requires a FIFO buffer to be associated with it. The MUSBHSFC has a RAM interface for connecting to a single block of synchronous single-port RAM (added by the user.) The FIFO buffer for end point 0 is fixed at 64 bytes. The other end point FIFO buffers may be from 8 to 8,192 bytes in size and can buffer either one or two packets. Separate FIFO buffers may be associated with each end point; alternatively, an IN and an OUT end point with the same end point number can be configured to use the same FIFO buffer. This can, for example, reduce the size of the needed RAM block. The MUSBHSFC function provides a USB 2.0 transceiver macrocell interface to connect to an 8-/16-bit high-/full-speed transceiver.
The MUSBHSFCD1 netlist features a 16-/32-bit VSIA standard basic virtual component interface for connecting to a processor bus. It has a RAM interface for connecting to the single block of synchronous RAM that is used for all the endpoint FIFO buffers. The device also offers support for DMA access to the endpoint FIFO buffers. The MUSBHSFCD1 function provides all the USB packet encoding, decoding and checking--interrupting the CPU only when end point data has been successfully transferred.
Device Utilization Example
Table 1 lists the typical device utilization results for the mega function.
| Table 1. Typical Device Utilization Results for the Megafunction |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| Logic Cells |
EABs (1) |
| APEX™ 20KC |
-1 |
6,217 |
0 |
50.18 MHz |
Netlist is a fixed configuration of a configurable core. |
Note:
- EABs = Embedded array blocks
Contact Information
For additional information, contact Mentor Graphics at:
Mentor Graphics
1001 Ridder Park Dr.
San Jose, CA 95131
Tel. (408) 487-7039
Fax (408) 487-7380
Email: mentor_ip@mentor.com (Netlist Sales)
URL: www.mentor.com/products/ip/index.cfm
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