from Digital Core Design
      |
Features
- Software compatible with industry-standard 68HC11
- FAST architecture, four times faster than the original implementation
- 10 times faster multiplication operations
- 16 times faster division operations
- 256 bytes of remapped System Function Register spaces (SFRs)
- De-multiplexed address and data bus to allow easy connection to memory
- Core can be used without I/O wrapper, so each peripheral function pins are separated from I/O port lines
- Ready pin allows core to operate with slow program and data memories
- Two power-saving modes: STOP, WAIT
- Fully synthesizable
- Static synchronous design with no internal tri-states
- No internal reset generator or gated clock
- Scan-test ready
Overview
The DF6811 is an advanced 8-bit microcontroller (MCU) core with highly sophisticated on-chip peripheral capabilities. The DF6811 soft core is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller and has an improved FAST architecture that is four times faster than the original implementation.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization | |||
Device |
Speed Grade | Utilized | Performance (fMAX) |
|---|---|---|---|
| Area | |||
| Cyclone® III | -6 | 3,574 logic elements (LEs) | 70 MHz |
| Cyclone IV | -6 | 3,575 LEs | 73 MHz |
| Stratix® IV | -2 | 2,522 adaptive look-up tables (ALUTs) | 135 MHz |
Deliverables
HDL source code package includes:
- VHDL or Verilog source code
- VHDL or Verilog test bench environment
- Active-HDL automatic simulation macros
- ModelSim® automatic simulation macros
- Full tests with reference responses
- Synthesis scripts
Encrypted megafunction package includes:
- EDIF or Text Design File (.tdf) netlist optimized for particular technology
- Core instantiation inside Quartus® II environment
- Symbol, include, assigments, and configuration files
- Compilation, simulation, and programming ready project
Each package includes:
- Technical documentation
- Installation notes
- HDL core specification
- Data sheet
- Example application
- Technical support
- Intellectual property (IP) core implementation support
- Three months of maintenance, including phone and e-mail support
For additional information, contact Digital Core Design at:
Wroclawska 94
41-902 Bytom
Poland
Tel: +48 32 2828266
Fax: +48 32 2827437
E-mail: aleads@dcd.pl
Website: http://www.digitalcoredesign.com
