DFPIC1655X - RISC Microcontroller
Features
- Software compatible with industry-standard PIC16C55X
- Modified architecture-two times faster than original implementation
- 35 instructions
- 14-bit wide instruction word
- Up to 256 bytes of internal data memory
- Up to 8 Kbytes of program memory
- 8-level-deep configurable hardware stack
- 8-bit timer/counter with programmable prescaler
- Two I/O ports
- Programmable watchdog timer
- Power-saving Sleep mode
- Three interrupt sources
- External interrupt
- Timer overflow interrupt
- Port B[7:4] change interrupt
- Fully synthesizable, static synchronous design with no internal tri-states
- No internal reset generator or gated clock
- Scan-test ready
- Technology-independent hardware description language (HDL) source code
Block Diagram
Figure 1 shows a block diagram of the function.
Description
The DFPIC1655X is a low-cost, high per-formance, 8-bit, fully static intellectual property (IP) core, binary-compatible with the industry-standard PIC16C554 and PIC16C558. It employs a modified RISC architecture (two times faster than original implementation).
The DFPIC1655X has enhanced core features, configurable hardware stack, and multiple internal and external interrupt sources. The separate instruction and data buses allow a 14-bit-wide instruction word with the separate 8-bit-wide data. The DFPIC1655X typically achieves a 2:1 code compression and an 8:1 speed improvement over other 8-bit microcontrollers in their class. The DFPIC1655X core has 13 I/O lines and an 8-bit timer/counter with an 8-bit programmable prescaller.
The power-down mode, Sleep, allows users to reduce power consumption. Users can wake up the controller from Sleep mode through several external and internal interrupt and reset. An integrated watchdog timer with its own clock signal provides protection against software lock-up.
The DFPIC1655X fits perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power-save mode makes this IP perfect for applications where power consumption is critical. The low logic element (LE) count in programmable devices makes this IP ideal for applications with space limitations. Low-cost, low-power, high performance, and ease of use make the DFPIC1655X very versatile even in areas where no microcontroller has been considered before.
Device Utilization Example
Table 1 lists the typical device utilization results for the megafunction.
| Table 1. Typical Device Utilization |
| Device |
Speed Grade |
Utilization |
Performance
(fMAX) |
Parameter Setting |
| LEs |
EABs |
| Stratix™ |
-7 |
2220 |
4 |
73 MHz |
Contact DCD |
| APEX™ 20KE |
-1 |
2239 |
8 |
54 MHz |
Contact DCD |
| APEX 20KC |
-7 |
2116 |
8 |
64 MHz |
Contact DCD |
| ACEX® |
-1 |
2142 |
4 |
41 MHz |
Contact DCD |
Deliverables
HDL source code package includes:
- VHDL or Verilog source code
- VHDL or Verilog test bench environment
- Active-HDL automatic simulation macros
- ModelSim® automatic simulation macros
- Full tests with reference responses
- Synthesis scripts
Encrypted megafunction package includes:
- EDIF or Text Design File (.tdf) netlist optimized for particular technology
- Core instantiation inside Quartus® II or MAX+PLUS® II environments
- Symbol, include, assigments, and configuration files
- Compilation, simulation, and programming ready project
Each package includes:
- Technical documentation
- Installation notes
- HDL core specification
- Data sheet
- Example application
- Technical support
- IP core implementation support
- Three months of maintenance, including phone and e-mail support
Contact Information
For additional information, contact Digital Core Design at: Wroclawska 94
41-902 Bytom
Poland
Tel: +48 32 2828266
Fax: +48 32 2827437
E-mail: info@dcd.pl
http://www.digitalcoredesign.com
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