Avalon Switch Fabric
The Avalon® switch fabric, Altera's parameterized interface bus used by the Nios® embedded processor, provides a set of pre-defined signal types with which a user can connect one or more intellectual property (IP) blocks. Altera's SOPC Builder system development tool automatically generates the Avalon switch fabric logic. The Avalon switch fabric logic often includes capabilities for data-path multiplexing, address decoding, wait-state generation, dynamic-bus sizing, interrupt-priority assigning, and advanced switch fabric transfers. Users can easily integrate their own IP blocks and peripherals with the rest of their Nios processor-based system.
The Avalon switch fabric requires minimal FPGA resources and provides fully synchronous operation. Its important and distinguishing features include:
For more information on the Avalon switch fabric, refer to the specification.
Simple Wizard-Based Configuration
An easy-to-use graphical user interface (GUI), Altera's SOPC Builder system development tool, guides the user through the process of adding peripherals, specifying master/slave relationships, defining memory maps, and more. The Avalon switch fabric architecture is generated automatically based on user input from the wizard GUI. An example screen shot is shown in Figure 1.
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More information about the revolutionary SOPC Builder system development tool is available on the SOPC Builder web page.
Simultaneous Multiple Masters
Nios developers can optimize their system data flow by creating system bus architectures custom-tailored to their application-specific bandwidth needs. The Avalon switch fabric supports simultaneous transactions for all bus masters and automatically includes arbitration for peripherals or memory interfaces that are shared among masters. Additionally, a direct memory access (DMA) peripheral can be used with any slave peripheral to provide bus-mastering capability.
In traditional bus protocols, a single arbiter controls communication between one or more bus masters and bus slaves. In such a system, there is a bandwidth bottleneck because only one master can access the system bus at a time. Figure 2 illustrates a traditional bus architecture in a processor-based system.
Figure 2. Traditional Bus Architecture
The Avalon switch fabric enables true simultaneous multi-master operation for maximum system performance, using a technique called slave-side arbitration. Slave-side arbitration determines which master gains access to the slave if multiple masters attempt to access the slave at the same time. Figure 3 illustrates an example configuration using the simultaneous multi-master feature of the Avalon switch fabric. In such a system, high-bandwidth peripherals, such as 100-Base-T Ethernet, can access data memory directly without halting the CPU. By allowing memory access that is independent of the CPU, the Avalon switch fabric optimizes data flow and maximizes system throughput.
Figure 3. Simultaneous Multi-Master Avalon Switch Fabric
Up to 4-Gbyte Address Space
Memory and peripherals may be mapped anywhere within the 32-bit address space. In other words, a CPU (or other bus master) has an addressable memory range of up to 4 Gbytes.
Synchronous Interface
All Avalon signals are synchronized to the main Avalon clock. This simplifies the relevant timing behavior of the Avalon switch fabric logic and facilitates integration with high-speed peripherals.
Built-In Address Decoding
The SOPC Builder-created Avalon switch fabric automatically generates chip-select signals for all peripherals (even user-defined peripherals), greatly simplifying the design of Nios processor-based systems.
Separate, dedicated address and data paths provide an extremely easy interface to on-chip user logic. User-defined peripherals are not required to decode data and address bus cycles.
Read & Write Transfers with Latency
The Avalon switch fabric can perform read and write operations with latency. Such latent transfers are useful because a master can issue a read or write request, move on to an unrelated task, and return to receive data later. This feature can also be useful for posting multiple read or write requests to a latent-aware slave. For example, this is often beneficial for instruction-fetch operations and DMA transfers in which access to sequential addresses is common. In these cases, the CPU or DMA master may prefetch expected data to reduce average access latency in synchronous memory.
Streaming Transactions
Streaming transactions with the Avalon switch matrix create open channels between streaming masters and streaming slaves to perform successive data transfers. These channels allow data to flow between the master-slave pairs as data becomes available. A master does not have to continuously access status registers in the slave peripheral to determine whether the slave can send or receive data.
Streaming transactions maximize throughput between master-slave pairs, while avoiding data overflow or underflow on the slave peripherals. This is especially useful for DMA transfers.
Dynamically Sized Peripheral Interface
Dynamic bus sizing allows Nios developers to use low-cost, narrow memory devices that do not match the native bus size of their Nios CPU. For example, a system configured with a 32-bit data path can easily integrate an 8-bit flash memory device. In such a system, the dynamic bus sizing logic automatically executes multiple bus cycles, if necessary, to fetch wide data values from the narrow peripheral. The SOPC Builder automatically adds the dedicated logic needed to perform re-sizing and alignment.
For more information regarding dynamic bus sizing, refer to the Nios Embedded Processor 32-Bit Programmer's Reference Manual and the Nios Embedded Processor 16-Bit Programmer's Reference Manual.
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