Need to boost performance? No problem. Hardware acceleration is as easy as using an FPGA's programmable logic to offload and accelerate tasks that are typically implemented in application software.
Want to automate hardware acceleration? Simply right-click to accelerate your performance-critical C-language software algorithms, and the tools will automatically convert them to hardware for you.
Read on to learn more about accelerating software in FPGAs. Nios® II developers typically use one of two main methods of hardware acceleration:
Hardware Accelerators
Hardware accelerators are blocks of logic that are either automatically generated by the Nios II C-to-Hardware Acceleration (C2H) Compiler or manually designed to offload specific tasks from the system processor. Many math operations are performed more quickly and efficiently when implemented in hardware versus software. SOPC Builder and the AvalonTM switch fabric support using hardware accelerators to boost the performance of software run on a Nios II processor. Among other things, hardware accelerators:
- Access main memory and other system resources with fully pipelined and memory latency-matched master ports that can sustain extremely high memory bandwidth
- Are controlled by the CPU through a slave port
- Have software wrapper functions for control from the CPU, and which substitute for original C code in the tool chain
Figure 1 shows a typical hardware accelerator, which has two master ports to the Avalon switch fabric (read and write). The accelerator uses direct memory access (DMA) components to execute bus read and write operations, and it has a control port to allow for processor control. Finally, in the center, the accelerator logic represents the engine that computes the designated algorithm.
Figure 1. Anatomy of a Typical Hardware Accelerator
Adding powerful capability to Altera's FPGAs, hardware accelerators can be implemented as complex, multi-cycle co-processors with pipelined access to any memory or peripheral in the system. They can utilize FPGA resources (such as on-chip memory and hard-macro multipliers) to implement local memory buffers and multiply-accumulate (MAC) circuits. Using as many master ports as necessary, they can initiate their own read and write operations and access any I/O pin in the system. Many Nios II developers have discovered that hardware accelerators are a great way to boost performance of their software code and take full advantage of the high-performance architecture of Altera® FPGAs.
Custom Instructions
Similar to hardware accelerators, custom instructions allow Nios II designers to increase system performance by offloading portions of the software code to hardware functions. Custom instructions, however, are implemented within the processor boundary, extending the CPU instruction set to accelerate time-critical software.
The configurable nature of Nios II processors enables designers to integrate custom logic directly into the arithmetic logic unit (ALU). Custom instructions let developers optimize software inner loops for applications such as digital signal processing (DSP), packet header processing, and computationally intensive applications, reducing complex operational sequences to a single instruction implemented in hardware.
Using custom instructions, designers can optimize their system performance in a way not possible with traditional off-the-shelf processors. Altera's SOPC Builder provides a graphical user interface that developers can use to easily import their own hardware design files to create custom instructions that are automatically integrated into the Nios II processor.
Nios II processor custom instructions provide:
- Up to 256 user-defined instructions
- Fixed and variable-cycle operation
- User-logic import wizard
- C and assembly language software macros
Figure 2 shows the flexibility of the custom instruction logic.
Figure 2. Custom Instruction Logic
For more details, see the Nios II processor handbook.
