EDA ACCESS Partner Profiles: Blue Pearl
Overview
Blue Pearl Software is a privately held EDA company that develops software to improve productivity of semiconductor chip design. Blue Pearl provides high-performance, innovative, automated tools to generate and validate critical timing and functional information early in the design cycle. Blue Pearl's solutions allow you to improve the quality of results, save time, and lower the cost of your chip design process.
Blue Pearl’s software is used by ASIC and FPGA designers early in the design flow, on high-level functional descriptions of an integrated circuit, to develop higher quality register transfer level (RTL) code and to automatically generate comprehensive and accurate timing constraints that significantly improve quality of results (QoR).
Incorporating Blue Pearl’s products in the design flow is easy as all inputs and outputs are industry standards. Customers benefit by substantially reducing costs that are incurred by electronic products entering the market with timing or functional design errors.
Tools
Table 1 lists design tools supporting Altera® devices.
| Table 1. Design Tools Supporting Altera Devices |
| Design Flow |
Tool Name |
Comments |
| Verification |
| Design Entry |
Indigo RTL Analysis |
Easy-to-use Linting tool for Verilog descriptions that has many functional design checks to catch issues that could take a very long time to simulate. Indigo identifies clock domain crossings and simulation/synthesis mismatches as well as dead-end states for FSMs. It finds combinational loops and other timing errors, checks for adherence to methodology rules (design, test, reuse), and is user programmable. |
| Cobalt Timing Constraint Generation |
Cobalt automatically generates timing exception constraints from the Verilog description. Cobalt reads Verilog and identifies the false and multi-cycle paths in the description and generates the SDC constraints for use with synthesis and physical layout tools. Cobalt also writes out assertions in PSL or SVA formats for use in simulation or formal verification tools. Cobalt can write constraints and assertions for timing exceptions that cross clock domains if the clock definitions are provided. The clock definitions can be read from an SDC file or entered directly into Cobalt. |
| Azure Timing Constraint Validation |
Azure automatically validates timing exception constraints that are provided in an SDC format for a Verilog description. This lowers the risk of using third-party intellectual property (IP) and legacy blocks that are not familiar to designers. Azure reads the Verilog and the SDC and validates correctly-specified constraints. If the constraint is incorrect, Azure reports the error and produces a test bench that can be used in a simulation environment to prove that the false path can be stimulated or the multi-cycle path can fire in a different number of cycles. |
| Synthesis |
Cobalt Timing Constraint Generation |
The timing exceptions that Cobalt generates are used at synthesis to significantly improve the QoR that achieves faster timing closure through physical implementation. |
| Azure Timing Constraint Validation |
The timing exception constraints validated by Azure are used at synthesis with a high level of confidence, to lower the risks of design implementation. |
| Verification |
Cobalt Timing Constraint Generation |
Cobalt writes out PSL and/or SVA assertions that can be added to test benches to improve verification coverage and can be used in formal verification tools to prove that the constraint is correct. |
| Azure Timing Constraint Validation |
Azure validates existing constraints for legacy blocks, IP, or designs so that the timing exception constraints can be used with a high level of confidence. |
Contact Information
For additional information, contact Blue Pearl at:
Blue Pearl Software, Inc.,
4677 Old Ironsides Drive, Suite 430
Santa Clara, CA 95054
Tel: (408) 961-0121
Email: info@bluepearlsoftware.com
URL: www.bluepearlsoftware.com
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