Overview
Bluespec delivers SystemVerilog-based ESL synthesis with no compromise (speed and area) register transfer level (RTL) for both FPGA and ASIC designers. With the only solution for control logic and complex datapaths, Bluespec's ESL synthesis toolset significantly accelerates hardware design and reduces verification costs by delivering:
- A greater than 50 percent reduction in time to verified netlist
- Less than 50 percent of the bugs compared to RTL design
Bluespec presents the hardware designer an exciting new way to implement a design with correct-by-construction control logic synthesis while retaining full control over the architecture and performance of the design. The toolset allows FPGA designers to significantly reduce design time, verification effort, and bugs that contribute to product delays and escalating costs.
Bluespec takes a high-level description, produces RTL, and is used across a range of circuits such as:
- Controllers, for example:
- Cache
- Memory
- DMA
- Serial
- Bus Converters
- Network Processors
- Physical (PHY) Layers
- Queuing Engines
- Sorting Queues
- Processors (RISC or CISC)
- Arbiters
- Pixel Processors
Bluespec design flexibility promotes:
- Accelerated Functional and Timing Closure
- Rapid Architecture Exploration
- Consistent Model and Implementation Delivery for Software Testing
- Unparalleled Re-Use
- Faster Derivatives
Tools
Table 1 lists Bluespec's tools supporting Altera® devices.
| Table 1. Design Tools Supporting Altera Devices | ||
| Design Flow | Tool Name | Comments |
|---|---|---|
| System Level | ||
| High-Level Synthesis | Bluespec Compiler |
Key features of the Bluespec Compiler are:
|
| Verification | ||
| High-Level Simulation | Bluespec Simulator |
Key features of the Bluespec Simulator are:
|
Contact Information
For additional information, contact Bluespec at:
Bluespec, Inc.
200 West Street,
Waltham, MA 02451-1121
Main: 781-250-2200
Sales:sales@bluespec.com
