EDA ACCESS Partner Profiles: Celoxica
Overview
The partnership between Celoxica and Altera has resulted in a co-design and high-level language design solutions for high-density PLDs devices such as Cyclone™, Stratix®, and Excalibur™. These design solutions are also optimal for the Nios® embeddable soft-core processor.
System-level EDA products from Celoxica provide designers with tools to optimize system performance and cost, while reducing design time by as much as 50 percent. The development flow with Altera enables designers to implement the design using the C programming language or hardware description language (HDL), and elevates the system partitioning and verification process to the beginning stages of the development cycle. This allows system designers to:
- Analyze hardware & software trade-offs
- Explore the design space coupled with super-fast simulation speeds
- Find the optimal hardware and software partition and repartition the design at any stage
- Integrate hardware and software components
- Perform co-verification
- Generate optimized hardware representations of the design or optimized register transfer level (RTL) from the C programming language to feed logic synthesis tools automatically
The Celoxica design environment is embodied in the DK Design Suite. It includes the powerful co-design and co-verification product, Nexus-PDK, which allows designers to simulate system functionality in mixed language descriptions, including C, C++, SystemC, Handel-C, MATLAB, VHDL, and Verilog.
Based on Celoxica's unrivalled expertise in high-level language synthesis, the DK Design Suite can synthesize optimized EDIF for Altera® devices from C-based descriptions or generate optimized RTL to feed logic synthesis flows.
Tools
Table 1 lists design tools supporting Altera devices.
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Table 1. Design Tools Supporting Altera Devices
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Design Flow
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Tool Name
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Comments
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System Level
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Hardware/Software
Partitioning and Co-Simulation
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Nexus-PDK
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The Nexus-PDK tool enables co-design and co-verification so engineers can explore design solutions, find optimal partitions for their system hardware and software, and co-simulate the C-based models with hardware RTL simulations. Nexus supports co-simulation with MATLAB, C, C++, SystemC, Handel-C, VHDL, and Verilog.
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High Level Design Tools
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DK Design Suite
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The Celoxica DK Design Suite consists of a single design environment that combines the flexibility of higher-level language design techniques with the capabilities of a powerful system-level co-design and co-verification. The DK Design Suite can synthesize optimized EDIF for Altera devices from C-based descriptions or generate optimized RTL to feed logic synthesis flows.
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C-Based IP Accelerator Tools
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DK Accelerator for SOPC Builder
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The Celoxica DK Accelerator for SOPC Builder design tools provides the design capability to create custom C-based components directly into the Altera SOPC Builder design flow. By using the SOPC Builder to automatically integrate processors and peripherals, the overhead of IP integration is reduced thus enabling maximum designer effort for the development of value-added system IP.
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Design Entry
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Design Entry & Rule Check
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Nexus PDK
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See the Nexus PDK description above.
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Synthesis
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DK Design Suite
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See the DK Design Suite description above.
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Verification
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Simulation
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Nexus PDK
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See the Nexus PDK description above.
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Contact Information
For additional information, contact Chris Sullivan at:
Celoxica Ltd.
66 Milton Park
Abingdon
Oxfordshire
OX14 4RX
United Kingdom
Tel: +44 (0) 1235 863656
Fax: +44 (0) 1235 863648
Email: Chris.Sullivan@celoxica.com or info.emea@celoxica.com
URL: www.celoxica.com
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