EDA ACCESS Partner Profiles: SynaptiCAD

SynaptiCAD offers a complete line of HDL and timing visualization tools for Altera^® devices:

TestBencher Pro generates VHDL, Verilog, and C++ test benches from graphical timing diagrams
Timing Diagrammer Pro is the industry’s most advanced timing diagram editor
VeriLogger Pro is a Verilog simulator with graphical stimulus generation
WaveFormer Pro is an FPGA design tool with an interactive HDL simulator

Table 1 lists design tools supporting Altera devices.

Design Flow	Tool Name	Comments
*Table 1. Design Tools Supporting Altera Devices*
System Level
High Level Design Tools	TestBencher Pro	TestBencher Pro is a graphical test bench generator that reduces the time required to create and maintain test benches.
Design Entry
Design Entry & Rule Check	TestBencher Pro	See description of Test Bencher Pro above
	WaveFormer Pro	WaveFormer Pro enables the designer to automatically determine critical paths, verify timing margins, adjust for reconvergent fan-out effects, and perform "what if" analysis to determine optimum clock speed.
	Timing Diagrammer Pro	Timing Diagrammer Pro has a modeless drawing and editing environment; delays, setups, and holds for performing timing analysis; time markers; seven graphical waveform states; virtual and group buses; and clocks with formulas.
	VeriLogger Pro	VeriLogger Pro is a complete design and verification environment for ASIC and FPGA designers.
Verification
Simulation and Timing Analysis	VeriLogger Pro	See VeriLogger Pro description above
	TestBencher Pro	See TestBencher Pro description above
	WaveFormer Pro	See WaveFormer Pro description above
	Timing Diagrammer Pro	See Timing Diagrammer Pro above

For additional information, contact Donna Mitchell at:

SynaptiCAD
520 Prices Fork Rd #C4
Blacksburg VA 24060 USA

Tel. 540-953-3390