EDA ACCESS Partner Profiles: Synplicity, Inc.

Table 1. Design Tools Supporting Altera Devices

System Level

Device Partitioning

Certify

Certify^®
Certify ASIC prototyping solution is the leading product for ASIC prototyping using multiple FPGAs. Certify software combines register transfer level (RTL) multi-chip partitioning with best-in-class FPGA synthesis. Using the Certify product makes ASIC prototyping significantly easier, shortens prototype development time, improves prototype performance, and enables faster time-to-market.

Design Entry

Design Entry & Rule Check

Synplify

Synplify^® FPGA Synthesis
The Synplify solution is a high-performance, sophisticated logic synthesis engine that utilizes proprietary Behavior Extracting Synthesis Technology (BEST) to deliver fast, highly efficient FPGA and CPLD designs. The Synplify product takes Verilog and VHDL Hardware Description Languages as input and outputs an optimized netlist in most popular FPGA vendor formats.

Synplify Pro

Synplify Pro^® Advanced FPGA Synthesis
High-density field programmable gate arrays (FPGAs) contain high-speed I/O, microprocessors, millions of logic gates, and operate at speeds in excess of 200 MHz. The Synplify Pro tool starts with all the features that made Synplify software the industry's most popular and robust synthesis product, and moves beyond by providing additional capabilities.

Synthesis

Synthesis

Synplify

See description of Synplify above

Synplify Pro

See description of Synplify Pro above

Physical Synthesis

Amplify FPGA Physical Optimizer

Amplify^® FPGA Physical Optimizer™
The Amplify Physical Optimizer product is the first and only proven physical synthesis tool designed specifically for programmable logic designers. The Amplify product performs simultaneous placement and logic optimization, and demonstrates an average of over 21% performance improvement, and over 45% improvement in some cases when compared with logic synthesis alone. The Amplify Physical Optimizer now includes a fully automated physical synthesis flow.

Verification

Timing Analysis

Synplify

See description of Synplify above

Synplify Pro

See description of Synplify Pro above

In-System Debugging

Identify

Identify™ RTL Debugger
The Identify product is the first and only software tool that allows FPGA designers and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification with RTL designs 10,000 times faster than RTL simulators, and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW designs. Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and the results are viewed directly in the RTL source code. The Identify tool can also save results in standard VCD format that can be used with most waveform viewers.