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主页 > 产品 > 设计软件 > EDA合作伙伴 > Verification 打印此页 订阅电邮新闻 Verification Verification tools support the following: Simulation (see Table 1) Timing analysis (see Table 2) Formal verification (see Table 3) In-system debugging (see Table 4) Table 1. Simulation EDA Vendor Tool Name Description Aldec Active HDL VHDL Verilog C/C++ EDIF Riviera High-performance VHDL Verilog Mixed simulation Altium nVisage VHDL simulation Protel Circuit simulation Cadence Incisive Single-kernel verification tool NC Desktop Family Verilog Desktop, VHDL Desktop, and NCSim Desktop for the Windows platform Celoxica Nexus PDK Co-verification Mentor Graphics® ModelSim® Verilog, VHDL, and Mixed-VHDL/Verilog simulator Visual Elite High-level C/C++ SystemC functional modeling and verification Simucad Design Automation Silos Verilog HDL logic simulation SynaptiCAD VeriLogger Pro Design and verification environment Synopsys VCS Simulator VCS MX Mixed-HDL simulator Table 2. Timing Analysis EDA Vendor Tool Name Description SynaptiCAD Timing Diagrammer Pro Timing diagram editor VeriLogger Pro Design and verification environment TestBencher Pro Graphical testbench generator WaveFormer Pro Optimal clock-speed analyzer Synopsys PrimeTime Static timing analyzer Table 3. Formal Verification EDA Vendor Tool Name Description Cadence Incisive Conformal Formal verification equivalency checker Mentor Graphics FormalPro Formal verification equivalency checker Synopsys Formality Equivalence checker Table 4. In-System Debugging EDA Vendor Tool Name Description Aldec Active HDL VHDL Verilog C/C++ EDIF Riviera High-performance VHDL Verilog Mixed simulation HDL Works HDL Companion Syntax checking and error tracing Synopsys VERA Testbench automation Telecom Workbench Telecom standards Synplicity Identify RTL debugging Temento Systems DiaLite On-chip instrumentation tool 给本页评分   相关链接 EDA Partners Listed by Design Flow EDA Partners Listed Alphabetically

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