Verification

Verification tools support the following:

Simulation (see Table 1)
Timing analysis (see Table 2)
Formal verification (see Table 3)
In-system debugging (see Table 4)

EDA Vendor	Tool Name	Description
*Table 1. Simulation*
Aldec	Active HDL	VHDL Verilog C/C++ EDIF
Aldec	Riviera	High-performance VHDL Verilog Mixed simulation
Altium	nVisage	VHDL simulation
Altium	Protel	Circuit simulation
Cadence	Incisive	Single-kernel verification tool
Cadence	NC Desktop Family	Verilog Desktop, VHDL Desktop, and NCSim Desktop for the Windows platform
Celoxica	Nexus PDK	Co-verification
Mentor Graphics^®	ModelSim^®	Verilog, VHDL, and Mixed-VHDL/Verilog simulator
Mentor Graphics^®	Visual Elite	High-level C/C++ SystemC functional modeling and verification
Simucad Design Automation	Silos	Verilog HDL logic simulation
SynaptiCAD	VeriLogger Pro	Design and verification environment
Synopsys	VCS	Simulator
	VCS MX	Mixed-HDL simulator

EDA Vendor	Tool Name	Description
*Table 2. Timing Analysis*
SynaptiCAD	Timing Diagrammer Pro	Timing diagram editor
	VeriLogger Pro	Design and verification environment
	TestBencher Pro	Graphical testbench generator
	WaveFormer Pro	Optimal clock-speed analyzer
Synopsys	PrimeTime	Static timing analyzer

EDA Vendor	Tool Name	Description
*Table 3. Formal Verification*
Cadence	Incisive Conformal	Formal verification equivalency checker
Mentor Graphics	FormalPro	Formal verification equivalency checker
Synopsys	Formality	Equivalence checker

EDA Vendor	Tool Name	Description
*Table 4. In-System Debugging*
Aldec	Active HDL	VHDL Verilog C/C++ EDIF
Aldec	Riviera	High-performance VHDL Verilog Mixed simulation
HDL Works	HDL Companion	Syntax checking and error tracing
Synopsys	VERA	Testbench automation
Synopsys	Telecom Workbench	Telecom standards
Synplicity	Identify	RTL debugging
Temento Systems	DiaLite	On-chip instrumentation tool

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