Quartus II Chip Editor
One of the toughest challenges that FPGA designers have faced to this point is implementing incremental engineering change orders (ECOs) late in the design cycle while maintaining timing closure. With the Quartus® II software's new chip editor, designers can view Altera® devices' internal structure and incrementally edit device resource functionality and parameter settings. The chip editor can also help designers document and manage ECOs.
Get a Detailed Design View
The chip editor can show hierarchical views of a design implemented in an Altera device (see Figure 1). Depending on the zoom level, the chip editor can display a design from a global field view, a more detailed logic array block (LAB) view, or a highly detailed logic element (LE) and routing view.
Figure 1. Chip Editor Hierarchical Views
Implement Changes in Minutes
The chip editor works directly on design netlists so a designer can implement device changes in minutes without performing a design compilation. Changes are restricted to a particular device resource to maintain timing closure in the remaining portions of the design. All changes have design rule checks on them to prevent users from making illegal edits.
Edit Device Resource Functionality & Parameters Easily
A designer can access the resource property editor from the chip editor to edit resource functionality and parameters. (Figure 2 shows resources used by a particular LE.) Designers can easily edit the look-up table (LUT) sum equation and change logic cell parameters to change the LE's functionality. The Quartus II software version 4.0 and later also allows designers to add or remove terms in the LUT sum equation to create or delete connections between LEs. The resource property editor can also be used to easily change I/O cell parameters and phase-locked loop (PLL) parameters.
Figure 2. Resource Property Editor
Use the Change Manager to Document & Manage Changes
All changes are documented in the chip editor change manager (shown in Figure 3). The change manager performs quick design rule checks on the design modifications and can be used to apply or remove individual design changes. The change manager can also export changes to tool command language (Tcl) scripts so changes can be recreated easily without updating hardware description language (HDL) source files.
Figure 3. Chip Editor Change Manager
Reduce Verification Time
Combining the SignalTap® II embedded logic analyzer with the chip editor drastically reduces design verification cycles. Engineers can use the SignalTap II embedded logic analyzer to identify design problems in-system and fix them within minutes with the Quartus II software chip editor.
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