Structured ASIC Design Flow
Designers can now use the same design tools, intellectual property (IP), and verification methodologies used for Altera® FPGAs to design for HardCopy® Stratix® structured ASIC devices. This web page provides an overview of the HardCopy design flow. The following resources are available for more detailed information:
ASIC Gain without the Pain
For the first time in the industry, the new HardCopy Stratix design flow enables designers to target a structured ASIC device from the beginning of a design cycle, and they can get predictable performance in a fraction of the time that it would take to develop an ASIC (shown in Figure 1). To reduce risk, HardCopy designs can be functionally tested in-system using a pin- and resource-compatible FPGA without any further development effort.
Figure 1. Quartus II Software & HardCopy Stratix Device Dramatically Reduce Time-to-Market vs. ASICs
Note to Figure 1:
- RTL = Register transfer level
The HardCopy Design Flow Advantage: Parallel System Development
Only HardCopy structured ASIC devices can be seamlessly functionally verified in-system using a pin- and resource-compatible FPGA device. HardCopy FPGA prototypes are developed seamlessly using the same design tools and IP used to develop the HardCopy structured ASIC devices. HardCopy designers can begin system validation using the FPGA protoptype devices and even begin shipping products using an FPGA. Other structured ASIC solutions and ASIC solutions require designers to wait for expensive prototype devices to perform in-system validation and often incur time-consuming and expensive re-spin costs.
Quartus II Software Makes Designing for HardCopy Easy
The Quartus® II software includes features to make designing for structured ASIC devices as easy as designing for an FPGA. When designing for HardCopy Stratix devices, designers can take advantage of all the Quartus II software FPGA design flow features, prototype the design in an FPGA to test for functional accuracy, and then easily produce all the files required by the HardCopy design center to produce HardCopy implementations of the design. Figure 2 shows a high-level view of the HardCopy Stratix front-end design flow.
Figure 2. HardCopy Stratix Front-End Design Flow
Some of the Quartus II software’s specialized HardCopy Stratix design features include:
- HardCopy Optimization Wizard——This feature is used to: optimize a design for a HardCopy Stratix structured ASIC device, generate a floorplan view of the final placement, and calculate fMAX performance.
- HardCopy Power Estimation Wizard—This feature is used to calculate power consumption for the HardCopy device implementation.
- Design Assistant—This performs design rule checking on designs to guarantee the design will operate correctly in the FPGA prototype and in the final HardCopy device implementation.
- HardCopy Files Wizard—This feature generates all the file deliverables that the Altera HardCopy design center needs to produce the final HardCopy device implementation.
Figure 3 shows the HardCopy design wizard selections available from the Quartus II software project menu.
Figure 3. Quartus II Software Project Menu Selections for HardCopy Design
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