LogicLock Block-Based Design
LogicLock™ block-based design is a new methodology available exclusively to Altera® Quartus® II software users. Using the LogicLock methodology, designs are created hierarchically: each module is designed and implemented independently and then imported into the top-level project. Productivity is increased because each design module needs to be optimized only once. During integration and system-level verification, the performance of each logic module is preserved. Figure 1 compares design flows with and without the LogicLock methodology.
Figure 1: LogicLock Design Flow Comparison
With the LogicLock design methodology, designers create LogicLock constraints and integrate the constraints into a larger design. LogicLock constraints can be used either with custom blocks of logic or with pre-verified intellectual property (IP) from Altera or AMPPSM partners. The LogicLock flow guarantees repeatable placement when implementing a module of logic in a current project or exporting the module to another project.
Benefits
The new LogicLock design methodology provides:
- Shorter design cycles with performance preservation
- Enhanced hierarchical design flow
- Optimized design reuse flow
- Efficient team design methodology
Shorter Design Cycles with Performance Preservation
By using LogicLock constraints, a module of logic needs to be optimized only once. After the constraints have achieved the target performance, back-annotation of the LogicLock region preserves that performance.
For example, designers can instantiate a PCI megafunction in a design and lock down placement and performance. Adding additional modules of logic or changing logic in other areas of the design will not impede the performance of the PCI core. The LogicLock flow reduces the number of design cycles required to complete a project.
Enhanced Hierarchical Design Flow
The LogicLock flow enables designers to maintain independent properties for each module and achieve performance quickly through the hierarchical region implementation. LogicLock methodology allows designers or groups of designers to independently work on the design, complete place-and-route, optimize, and verify an individual design module. At the integration phase, only the total system needs to be verified. The placement and performance of individual modules is preserved.
Optimized Design Reuse Flow
LogicLock constraints can be imported. Because the LogicLock methodology allows a single constrained design module to be imported into multiple designs, design reuse is easy. Figure 2 shows a design module that an engineer developed independently being used in more than one project—with the same performance in each implementation.
Figure2: LogicLock Design Reuse
LogicLock Regions
LogicLock regions give designers control over placement. These regions provide the framework for true hierarchical designs where changes to one module of a design will not have any impact on the performance of other modules in the design. The properties that control how a LogicLock region behaves are described in Table 1.
| Table 1: LogicLock Region Properties |
| Property |
Options (1) |
Behavior |
| State |
Floating Locked |
Floating regions allow the Quartus II software to determine the region's location on the device. Locked regions represent user-defined locations of a region and are illustrated with solid line boundary in the graphical floor plans. A locked region must have a fixed size. |
| Size |
Auto
Fixed |
Auto-sized regions allow the Quartus II software to determine the appropriate size of a region given its contents. Fixed regions have a user-defined shape and size. |
| Reserved |
Off
On |
The reserved property allows a user to define whether the resources within a region can be used for entities that are not assigned to the region. If the reserved property is on, only items assigned to the region may be placed within its boundaries. |
| Enforcement |
Hard
Soft |
Soft regions give more deference to timing constraints and allow some entities to leave a region if it improves the performance of the overall design. Hard regions do not allow contents to be placed outside of the boundaries of the region. |
| Origin |
Any floorplan location |
The origin defines the top left hand corner of the LogicLock region's placement on the floorplan. |
Note:
1. Default assignments are floating, auto, off, and hard, respectively.
Figure 3 shows the Quartus II timing closure floorplan editor, as displayed in the Quartus II software, showing floating location and size regions and the connectivity between those regions. Designers can easily drag and drop hierarchy components into LogicLock regions using the floorplan editors or the LogicLock regions window.
Figure 3: Timing Closure Floorplan Editor
Hierarchical Regions
LogicLock regions can have "parent" and "child" region relationships, as shown in Figure 4. If you move the parent region, the child region will also move. The child region can float in the parent region or have a fixed placement relative to the origin of the parent region.
These regions can improve the performance of a given module. A design can be placed into a LogicLock region and then performance-critical parts of the design hierarchy can be further constrained to a smaller child region to improve performance.
Figure 4: Parent & Child Regions
Stratix II & Stratix Devices Designed for Block-Based Design
Altera Stratix™ II & Stratix devices include continuous routing lines to support and enhance the LogicLock block-based design methodology. This technology ensures that the same routing and clocking resources are available to a predefined design block regardless of where it is placed within a device to enable fast, deterministic performance. Deterministic performance allows designers to use the LogicLock incremental design methodology to develop intellectual property (IP) libraries of data processing and I/O functions that can be easily reused in any future project using Altera Stratix II and Stratix devices.
Third-Party Synthesis Support
Any third-party synthesis tools can be used in LogicLock design flows, including:
- Synplicity® Synplify® tools
- Mentor Graphics® Precision™ and LeonardoSpectrum™ tools
- Synopsys FPGA Express and FPGA Compiler II tools
LogicLock Device Support
LogicLock block-based design is included in the Quartus II software version 4.0 and later for these device families:
- Cyclone™ II
- Cyclone
- Stratix II
- Stratix
- MAX® II
- Stratix GX
- APEX™ II
- APEX 20K
- APEX 20KE
- APEX 20KC
- Excalibur™
Technical Literature
The following technical literature is available to help you learn more about LogicLock incremental design flows:
|
文档资料
> 
