Xilinx-to-Altera Design Migration
The Quartus® II design software provides a complete and easy-to-use design environment for Altera® devices. AN 307: Altera Design Flow for Xilinx Users helps designers familiar with Xilinx software learn to perform FPGA design flows quickly using the Quartus II software and begin targeting Xilinx designs to Altera devices. Version 2 of this application note has added support for modular executables and double-data rate (DDR) I/O conversion.
Basic Design Flow Comparison
Altera design software addresses the basic FPGA design flow as shown in Table 1.
| Table 1. Typical FPGA Design Flow Addressed by Xilinx & Altera Software |
| Design Flow |
Xilinx Software Feature |
Altera Software Feature |
| Project Creation |
|
- Quartus II New Project Wizard
|
| Design Entry & Synthesis |
- ISE HDL Editor
- Schematic Entry
- CORE Generator
- Xilinx Synthesis Technology (XST) or Third-Party EDA Synthesis
|
- Quartus II Text Editor
- Schematic Editor
- MegaWizard® Plug-In Manager
- Integrated Synthesis or Third-Party EDA Synthesis
|
| Constraints & Assignments |
|
- Quartus II Assignment Editor
|
| Design Compilation |
- ISE Design Implementation
|
|
| Timing Analysis |
|
- Quartus II Timing Analyzer
|
| Simulation |
- ModelSim® Xilinx Edition II (MXE II)
|
- Quartus II Simulator or ModelSim-Altera
|
Xilinx ISE vs. Altera Quartus II Timing Analysis Differences
Most hardware designers who are qualifying FPGA performance normally run push-button software benchmarks of FPGAs from different vendors to determine which FPGA provides the largest margin on their timing requirements. Unfortunately, different timing analysis tools have different default behaviors; hence, out-of-the-box compilations will not produce equivalent or fair performance comparisons.
The Performing Equivalent Timing Analysis Between Altera Quartus II & Xilinx ISE White Paper covers the differences in timing analysis between Xilinx ISE and Altera Quartus II software and outlines a procedure on how to set the tools to provide equivalent performance comparison.
In general, the Quartus II timing analyzer calculates all possible register-to-register and complex clock structures using worst-case-possible assumptions. Since many of these complex structures are not analyzed by the Xilinx ISE tool, the comparison can unfairly penalize the Quartus II software’s performance. Adjusting the Quartus II setting to perform equivalent timing analysis to that of ISE will ensure that a fair comparison is made by analyzing the same paths in the circuit.
Step-By-Step Design Flow & Conversion Help
To help designers become familiar with the Quartus II software and to target Xilinx designs to Altera devices, Altera offers AN 307: Altera Design Flow for Xilinx Users. This document consists of two parts:
- Part 1: The Quartus II Approach to FPGA Design—Helps Xilinx designers become familiar with the Quartus II software by showing how to perform a basic FPGA design flow using Quartus II procedures instead of the equivalent Xilinx software procedures.
- Part 2: Xilinx-to-Altera Design Conversion—Details design file conversion procedures, including:
- Identifying design hierarchy
- Converting primitives and intellectual property (IP) cores
- Migrating design constraints
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