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主页 > 产品 > 设计软件 > 设计流程 > 验证与仿真 > SignalTap II Embedded Logic Analyzer 打印此页 订阅电邮新闻 SignalTap II Embedded Logic Analyzer The SignalTap® II logic analyzer is a second-generation system-level debugging tool that captures and displays real-time signal behavior in a system on a programmable chip (SOPC), giving engineers the ability to observe interactions between hardware and software in their system designs. Available exclusively in the Quartus® II software, the SignalTap II logic analyzer supports the highest number of channels, sample depth, and clock speeds of any embedded logic analyzer in the programmable logic market. The Quartus II software versions 4.0 and later also provides designers with a graphical interface to define custom-trigger-condition logic to provide greater accuracy and enhances the ability to isolate problems. Figure 1 shows the components of the SignalTap II embedded logic analyzer. The SignalTap II embedded logic analyzer does not require any external probes or changes to user design files to capture a design's state of internal nodes or I/O pins. Figure 1: SignalTap II Components SignalTap II Embedded Logic Analyzer Overview Running at speed under real-world system conditions is the ultimate testbench for engineers who want to see the active processes within their design as it operates. The SignalTap II embedded logic analyzer offers designers the ability to capture the state of internal nodes or I/O pins while the device is running in-system and at system speed. The SignalTap II embedded logic analyzer software can now be used in environments with multiple devices in a single JTAG chain, in combination with multiple logic analyzer megafunctions in each device in that JTAG chain. The following components are required to perform logic analysis with the SignalTap II embedded logic analyzer: Quartus II design software Soft embedded core megafunctions that are inserted into the device SignalTap II logic analyzer megafunction SignalTap II hub (automatically installed when an engineer chooses the SignalTap II logic analyzer in the Quartus II software) Download cable USB Blaster download cable ByteBlasterMV™ download cable ByteBlaster™ II download cable MasterBlaster™ download cable Device under test Captured data is stored in the device's memory blocks and streamed out to the Quartus II software waveform display using a USB Blaster, ByteBlasterMV, ByteBlaster II, or MasterBlaster communications cable. Table 1 summarizes the features and benefits of the SignalTap II embedded logic analyzer. Detailed descriptions of these features and benefits can be found on the SignalTap II Feature Descriptions web page. Table 1 SignalTap II Features & Benefits Feature Benefit Multiple logic analyzers in a single device Supports multiple clock domains in a single device Multiple logic analyzers in multiple devices in a single JTAG chain Allows multiple devices with multiple clock domains to be analyzed Up to 10 basic or advanced trigger levels for each analyzer  Allows for more complex data capture commands to be given to the logic analyzer, providing greater accuracy and problem isolation. Version 4.1 adds support for event counter trigger conditions. Flexible buffer acquisition modes Each trigger can be set up to sample at different ranges relative to the triggering event, in circular or segmented modes, which allows more accurate data collection Up to 1,024 channels in each device Enables sampling many signals and wide bus structures, and allows for a great deal of data collection to locate problems Up to 128K samples in each device Provides sufficient capacity for any practical application Clock support up to 200 MHz Allows for sampling of design data at system frequency Ability to incrementally add nodes, change signal selection and change trigger conditions without a full recompilation Allows user to change which nodes are monitored without a full design recompilation Lock mode to prevent recompilations Prevents SignalTap II configuration changes that will cause the need for a design recompilation No-cost stand-alone viewer  Allows easy deployment of in-system logic analysis capabilities to multiple lab locations or field service personnel Mnemonic and radix tables Label signals with true signal names from software source to assist in identification of problem source Multiple bus display formats Makes viewing and analyzing buses easier (now includes bar chart and line chart display options for captured data) Export data in multiple file formats Allows other verification tools to be used to analyze captured data Resource usage estimator Provides estimate of logic and memory device resources used by SignalTap II embedded logic analyzer configurations Auto detection of devices in JTAG chain Confirms connection to device before attempting to initiate data capture Auto detection of programming hardware Confirms connection to device before attempting to initiate data capture Ability to print waveforms Prints captured waveforms for reporting Vendor-independent application program interface (API) for Source-Level Debugging Tools Allows third-party software to utilize SignalTap II resources User-friendly interface Easier-to-use with status monitors to guide users through operation SignalTap II Device Support SignalTap II logic analyzers can now be used with the following device families: Cyclone™ devices Stratix® devices Stratix GX devices Excalibur™ devices APEX™ II devices APEX 20KE devices APEX 20KC devices APEX 20K devices Mercury™ devices Related Links On-Chip Debugging section of the Quartus II Software Handbook SignalTap II Features  给本页评分   相关链接 Download Design Debugging Using the SignalTap II Embedded Logic Analyzer handbook chapter Download the On-Chip Debugging section of the Quartus II Handbook     注册索取最新邮件通知

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