What's New in Quartus II Software Version 4.1
The Quartus® II software now delivers the lowest development costs for advanced system-on-a-programmable chip (SOPC) designs, including Altera’s new low-cost Cyclone™ II FPGAs. Version 4.1 includes new verification, optimization, and ease-of-use features that reduce design time and cost by up to 40 percent.
The Quartus II software now features unique leadership advantages in:
Extending Altera's Software Technology Leadership
The Quartus II software version 4.1 adds support for the Cyclone II FPGA family and the following new verification, optimization, and ease-of-use features:
Verification
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In-System Updating of RAM/ROM and Constants (PDF) Engineers can now easily perform “what if” experiments in-system in just seconds. Quartus II software enables FPGA memory contents and design constants to be updated in-system without recompiling a design or reconfiguring the rest of the FPGA.
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Technology Map Viewer (PDF) Designs can now be debugged in Quartus II software after the synthesis step, at a detailed level, by viewing a logical representation of the design implementations mapped into Altera ® device primitives. Once the fitting and timing analysis steps have been performed, critical timing paths and timing information can be highlighted in the technology map viewer display. Users can cross probe from timing analysis and other Quartus II tools to the technology map viewer, or from the technology map viewer to design source files, the floorplan editor, or Quartus II chip editor for design optimization.
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SignalTap® II Embedded Logic Analyzer Enhancements (PDF) The free Quartus II software now includes device configuration and the SignalTap II embedded logic analyzer, allowing easy deployment of in-system logic analysis capabilities to multiple lab locations or field service personnel. The advanced trigger feature now includes an event counter trigger condition function.
Optimization
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New Resource and Timing Optimization Advisor ToolsThese new tools provide specific advice to improve resource utilization or design timing performance based on the current design project settings and assignments, and provide links to software features to implement the proposed suggestions. Multiplexer Optimizations to Reduce Area Use up to 20 Percent (PDF)
Designers using the Quartus II integrated synthesis feature can now reduce device area usage up to 20 percent to fit into a smaller device and save cost. A new optimization technique optimizes multiplexer use to take advantage of Altera FPGA architectural features.
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- Stratix® II Physical Synthesis Optimization (PDF)
Physical synthesis optimizations now provide an average of 9 percent higher performance for Stratix II designs on top of the 50 percent performance gain delivered over Stratix designs compiled without using physical synthesis.
Ease-of-Use
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Easier Access to Altera MegaCore® Functions
Altera subscriptions now include the MegaCore IP Library and Nios® II embedded processor, evaluation edition, CDs. These CDs allow you to evaluate all of Altera's MegaCore design-ready IP functions in hardware before purchasing a license for the IP.
- Version Support (PDF)
Version support gives designers the ability to easily experiment with different versions of design source files and settings. This feature complements the previously introduced revisions feature that allowed designers to maintain separate settings.
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Import/Export Assignments in CSV Format
Engineers can now easily transfer assignments between Quartus II software and Excel spreadsheets using the CSV format. This capability can aid in transferring pinout information between PCB design software packages that support interfaces with Excel spreadsheets.
Quartus II Technical Resources Updated for Version 4.1
Expanding Quartus II Device Support
The Quartus II software version 4.1 adds support for Cyclone II devices—the lowest-cost FPGAs ever. The Quartus II software now supports the following device families:
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