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主页 > 产品 > 设计软件 > 产品 > Quartus II Software & Quartus II Web Edition Software Feature Comparison 打印此页 订阅电邮新闻 Quartus II Software & Quartus II Web Edition Software Feature Comparison The no-cost Quartus® II Web Edition software includes most of the features included in the Quartus II software subscription and everything needed to design for Altera's latest CPLD and low-cost FPGA families. Quartus II Web Edition software also includes support for entry-level members of Altera's high-density FPGA families. Quartus II subscription software offers: Support for all Altera® high-density FPGAs Support for HardCopy® Stratix® structured ASIC devices ModelSim®-Altera simulation software Additional productivity features Table 1 includes a detailed comparison between Quartus II software included in Altera software subscriptions and the Quartus II Web Edition software. Table 1. Version 4.1 of Quartus II Software & Quartus II Web Edition Feature Comparison Feature Quartus II Software Quartus II Web Edition Software Availability CD-ROM No-cost from the Download Center section of the Altera web site, and on the Quartus II Software Starter Suite CD-ROM Licensing Perpetual 150 days Device Support All ACEX® 1K, APEX™ 20K30E, APEX 20K60E, APEX 20K100E, APEX 20K160E, APEX 20K200C, APEX 20K200E, APEX II EP2A15, Excalibur™ EPXA1, Stratix™ II EP2S15, Stratix EP1S10, Cyclone™, Cyclone II, FLEX 10K®, FLEX® 10KA, FLEX 10KE EPF10K30E, FLEX 10KE EPF10K50S, FLEX 10KE EPF10K100E, FLEX 10KE EPF10K130E, FLEX 10KE EPF10K200S, FLEX 6000, MAX® II, MAX 3000A, MAX 7000B, MAX 7000S, MAX 7000AE MAX+PLUS® II Look & Feel Yes Yes RTL Viewer & Technology Map Viewer Yes No LogicLock™ Regions & Custom Regions Yes No Timing Closure Floorplan Yes Yes Assignment Editor & I/O Checking Features Yes Yes Chip Editor Yes Yes Netlist & Physical Synthesis Optimizations Yes No Timing & Resource Optimization Advisors Yes Yes Power Estimation Feature Yes Yes Project Archive Yes Yes ModelSim®-Altera Software Yes No Tcl(1) Scripting Support Yes Yes Fast Fit Yes Yes SignalTap® II Logic Analyzer Yes Available if the TalkBack feature is enabled. SignalProbe™ Feature Yes Available if the TalkBack feature is enabled. STAMP Models, Toolnet Yes Yes Save Intermediate Synthesis Results Yes Yes SOPC Builder Yes Yes Design Assistant Yes Yes HardCopy Tools Yes No Advanced Tutorials Yes No Virtual I/O Pins Yes No Device Migration Yes Yes Enable/Disable Messages Yes Yes IBIS Model Generation Yes Yes FIFO(2) Partitioner Megafunction Yes No Testbench Generation from VWF Files, Testbench Template Generation Yes Yes Notes to Table 1: 1. Tcl = Tool command language 2. FIFO = First-in first-out More information is available in the Design Software & Development Kit Selector Guide.  给本页评分

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