DSP Builder—Advanced Blockset with Timing-Driven Simulink Synthesis
DSP Builder is the leading synthesis technology for quickly and effortlessly implementing Simulink designs in the high-performance FPGA platform. With the 8.0 release of the DSP Builder tool, Altera has added a number of new Simulink blocksets—called the Advanced Blockset library—that vastly improves your productivity, especially for the synthesis of multi-channel designs.
The DSP Builder Advanced Blockset library adds new blocks and includes a unique synthesis technology that optimizes the high level, un-registered netlist into pipelined RTL targeted and optimized to your chosen device and desired clock rate. The synthesis technology automatically adds pipelined stages and registers to meet the system-level design constraints you set.
You can specify your desired clock frequency, number of channels, and other top-level design constraints. The generated RTL is automatically pipelined to achieve timing closure. By analyzing the system-level constraints, the tool also optimizes folding, that is, time division multiplexing to achieve optimum logic utilization, with no manual RTL tweaking.
The synthesis technology also allows you to easily increase or decrease the number of channels—for example, in your FIR filter or digital up conversion signal chain—simply by using a parameter file within the Simulink design. DSP Builder adds the required time division multiplexing control logic and generates the update RTL in a matter of minutes. The resulting RTL has performance similar to hand-optimized HDL.
The hardware is written out as plain text VHDL, along with scripts that integrate with the Quartus® II software for push-button compilation and the ModelSim® simulator for functional verification.
The combination of these features allows you to create a resource optimized, high-performance implementation without prior FPGA experience. This design can be retargeted on a variety of FPGA families.
The advanced blockset includes not only the high level intellectual property (IP) cores, but also primitive building blocks that allow you to build your custom algorithms. Many example designs are available that give you a starting point and help illustrate your design possibilities.
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