This guide highlights and explains Altera's online design and support resources. The information is divided into four main sections to quickly guide you to resources that can help you with your product development.
Information to help you select the right devices and development tools
- Product Literature
Our literature and technical documentation section lists handbooks (that include data sheets), application notes, user guides, manuals, pin connection guidelines, pin-out files, errata sheets, release notes, reliability reports and more. You'll find product information, like our Product Selector Guides, end market and corporate literature, as well as documentation on our FPGA, CPLD and ASIC devices and our development software, intellectual property (IP) cores and technology. You can also request literature services such as subscriptions to weekly Technical Updates on new or changed documents, eNewsletters and email announcements for updates on Altera® products, training, upcoming events and more.
- Design Software Tools
Product information on Altera's design suite, including Quartus® II development software Subscription Edition and Web Edition (see Quartus II Subscription Edition vs. Web-Edition (PDF) for comparison), SOPC Builder, ModelSim®-Altera software simulator, the Nios® II Embedded Design Suite, and DSP builder.
- Devices
Product information on each Altera device series. You can use the left column navigation bar to see a summary of features and capabilities and descriptions about each device series. Or you can select a family in the series from the listings on the page. For example, you can view the About Stratix® Series page or go directly to information on the Stratix IV FPGA family.
- Webcasts
Short view-on-demand presentations about our FPGA, CPLD, and ASIC devices, industry topics, and related design software and intellectual property (IP).
- Example Designs
Ready-to-use design examples to deliver efficient solutions to design problems. Use these examples to instantiate individual building blocks for use in a system design. For example, variations of external memory controller applications targeting Stratix® and Cyclone® FPGA families. Additional design examples can be found as associated with Application Notes and User Guides.
An index of complete system reference designs using Altera® intellectual property (IP) cores and tools: PCIe, SRIO, SDI, Triple-Speed Ethernet and other high-speed interfaces, memory controllers, embedded processors and digital signal processing (DSP). Downloadable with an Altera.com account. ![]()
- End Market Solutions
High-level, end market solutions for automotive, computer and storage, industrial, military, wireless, broadcast, consumer, medical, test & measurement and wireline applications.
- Technology Center
Introductory and in depth technical materials covering Altera® technology, including: transceiver portfolio and architecture, single-ended and differential I/O standards, the Signal Integrity Center, and solutions for digital signal processing (DSP), embedded processing, and external memory interfaces.
- Intellectual Property (IP)
A searchable database of Altera IP cores, related development kits, and reference designs, along with IP certification and licensing information. For a free in-system evaluation of Altera® and partner IP see AN 320: OpenCore Plus Evaluation of Megafunctions (PDF). You can also use the Transceiver Protocol Support selector guide to help select the right device for a chosen application.
- System Building
Design embedded systems with the Quartus® II development software and SOPC Builder tool. Build and simulate DSP systems using MathWorks/Simulink-to-FPGA DSP Builder design tool.
- Development Kits
Wide range of Altera and Partner development kits to address a variety of applications. Many development kits feature a standard host interface that accepts High Speed Mezzanine Cards (HSMC) daughter cards. Applications include PCIe, Ethernet, DVI, and more.
- Design and Support Services
Learn about Altera and Partner Professional design services to assist you in your product design.
- Buy Online
Online store for Altera devices, tools, development kits, programming hardware and cables.
Prepare to design with Altera® products.
- Download Center
Download Quartus® II software tools (latest and legacy), Nios® II Embedded Design Suite, ModelSim®-Altera, intellectual property (IP), license daemons, Gerber files and PCB footprints, SPICE and IBIS models, device programming software, and more.
- Get a License
Review licensing options and get a license for software, intellectual property (IP), and development kits for products you have downloaded or purchased from Altera. Requires and Altera.com account to access. ![]()
- Installation and Licensing Support
A central repository for installation and licensing support documentation. Refer to Altera Software Installation and Licensing (PDF) or use the licensing troubleshooter as a step-by-step diagnostic tool.
- Altera Training Resources
- Training Curricula
- Instructor-led Training
- Online Training (Free)
- Online Demonstration Center (Free)
Choose the training format, topic, and location. Use search courses to focus your selection. You can also view training partners outside of North America. Note, an Altera.com account is required to register for courses. ![]()
Series of courses for targeted designers – FPGA, CPLD, ASIC, embedded systems, ASIC-to-FPGA, digital signal processing (DSP), and system-on-a-chip (SOC).
In depth instructor-led training, typically with hands-on exercises.
Review the technical training catalog for free online training on topics ranging from tool usage to digital signal processing (DSP) filters, DDR implementation, and more.
An online demonstration center providing quick, free demonstrations to introduce Quartus® II software tools and Nios® II Processor embedded tools to new users.
Help for every phase of product development
- Design Phase
- Design Flows
- System Design Tools
- Quartus II Design Checklist
- Pin Connections
- Pin-Out Files for Altera Devices
- Device Pin Connections Guidelines
- Schematic Review Worksheet
- Board Design and Signal Integrity
- Power Management Resources
- Power Distribution Network (PDN) Tool
- Board Design Guidelines
- Board Design and IO Resources
- Signal Integrity Center
- External Memory Interfaces
- Phase-Locked Loop (PLL) Management
- HardCopy Design
An overview of the design flow for FPGA, CPLD, HardCopy® ASIC, DSP, and how to get started with Nios® II processor and Nios II Embedded Design Suite (EDS) development tools.
Reference materials and support for Nios® II embedded processing systems, SOPC Builder and digital signal processing (DSP) support including links to development kits and reference designs.
Thorough checklist for design planning, implementation, optimization and timing closure, I/O planning and constraints, PowerPlay Early Power Estimator (EPE), Quartus II PowerPlay power analysis and optimization, and on-chip debug (OCD).
Files listing Altera® device pin-out descriptions. There are up to three types of files for each device: Portable Document Format Files (.pdf), Text Files (.txt), and Microsoft Excel Files (.xls).
Altera recommended pin connections for each device. Note: You need to apply simulation results to the design to verify proper device functionality.
Schematic Review Worksheets for selected Stratix® II, Stratix III, Stratix IV, Cyclone® III and Arria® II FPGAs to assist you in reviewing schematics and tracking deviations from Altera's Device Pin Connections Guidelines.
Power management resources for estimating power at various stages of your design. Early Power Estimator (EPE) tools are for use before or during the design process to estimate power usage. The PowerPlay power analyzer tools are for accurate power estimation after the design is complete.
Graphical tool used with all Altera® FPGAs to optimize the board-level PDN. Link includes a dedicated PDN tool for Stratix IV FPGAs.
Consolidated information on all aspects of board design, including transceiver design, PDN, power dissipation and thermal management, simultaneous switching noise (SSN), PCB layout, signal integrity, JTAG debugging and configuration, external memory controllers, and more.
Board design resources and I/O management for users of the Quartus® II development software tools.
IBIS Models, SPICE Models, board-level and device-level signal integrity tools, simultaneous switching noise (SSN) estimator, training, and partners.
Complete memory interface design solutions for high-speed memory and external memory interface design examples.
Summary and comparison matrix of PLL resources and features available in Stratix and Cyclone device families.
Summary and comparison matrix of HardCopy® series ASICs and links to the Hardcopy IV ASIC family available with 6.5+ Gbps transceivers.
- Implementation Phase
- Configuration and Programming
- Design Entry and Planning
- Advanced Synthesis Cookbook
- Synthesis and Netlist Viewers
- Scripting
- Incremental Compilation
- Design Optimization
- Timing Analysis
- TimeQuest
- Switching to TimeQuest (PDF)
Summary of the configuration schemes supported by Altera devices and links to all resources and reference materials.
Guidelines on planning and structuring your design, as well as details about managing metastability in your design, and HDL coding styles.
PDF containing a collection of circuit building blocks and related discussions. Download also the advanced synthesis design files from manuals.
Comprehensive command-line and Tcl design flows.
How to use incremental compilation to segment your design into logical design partitions allowing top-down and bottom up design methodologies. Save compilation time in top-down and facilitate team work in bottom-up.
Optimize a design for area and timing. Resources to help with design optimization, physical synthesis, and the Design Space Explorer (DSE).
Static timing analyzer, TimeQuest, supports the industry-standard Synopsys Design Constraints (.sdc) format. Use the Quartus® II TimeQuest Timing Analyzer Cookbook (PDF) for a collection of scenarios, guidelines and recommendations.
Benefits and process of Switching to the Quartus® II TimeQuest Timing Analyzer (PDF) from the Quartus II Classic Timing Analyzer.
- Verification Phase
- Simulation and Verification
- On-Chip Debug
A collection of simulation and formal verification resources to help you understand the tools Altera supports, documents and design examples showing how to use these tools, and step-by-step diagnostic tools to help solve common problems.
A resource center for tools that allow real-time capture of internal nodes in your design. Plus Quick Design Debugging Using Signal Probe (PDF) and Design Debugging Using the SignalTap II Embedded Logic Analyzer (PDF).
Troubleshoot common problems.
- Knowledge Database (KDB)
Most recent solutions, known issues, troubleshooters, and self-help tools. Also access to advanced search, search tips, and the KDB Browser to search solutions by product category, area, and sub-area.
- Troubleshooters
Step-by-step diagnostic tools to solve common technical problems, including licensing, ModelSim® software simulation, timing analysis, PLL loss of lock, FPGA configuration, JTAG configuration and ISP, parallel flash loader (PFL), Jam, JBC and SVF programming.
- Altera Forum
The Forum brings Altera users together to learn from each other. At the Altera Forum, you can share projects, news, and ideas related to Altera® products.
- Nios Forum
The Nios Forum is the center where users can share ideas about the Nios II processor and embedded operating systems.
- Nios Community Wiki
A community for Nios II users to collaborate on user guides, design tips, and frequently asked questions.
- Design and Support Services
Learn about the professional design and support services offered by Altera and Altera partners.
- mySupport
Submit a service request (SR) to an applications engineer. Requires and Altera.com account to access. ![]()
- Contacting Altera
Altera contact information, including sales offices, distributors and representatives, plus corporate office addresses, telephone numbers, and email addresses.
NOTE:
Indicates an Altera.com account is required to access the information.
