文档资料: Arria II 器件

文档资料中文版

一般器件文件

采用带有收发器的全系列40-nm FPGA 和ASIC 实现创新设计 (1.0版, 2009年2月, 1.25mb)
在40-nm工艺节点实现世界上最先进的定制逻辑器件 (1.1版, 2009年2月,855kb)

文档资料英文版

PowerPlay Early Power Estimator

Arria II Device Handbook (21 MB)

Arria II Device Handbook Volume 1: Device Interfaces and Integration (ver 4.3, Dec 2011, 11 MB)

Section I. Device Core for Arria II Devices

Chapter 1. Overview for the Arria II Device Family (ver 4.3, Dec 2011, 397 KB)
Chapter 2. Logic Array Blocks in Arria II Devices (ver 2.0, Dec 2010, 739 KB)
Chapter 3. Memory Blocks in Arria II Devices (ver 3.2, Dec 2011, 1 MB)
Chapter 4. DSP Blocks in Arria II Devices (ver 4.0, Dec 2010, 1 MB)
Chapter 5. Clock Networks and PLLs in Arria II Devices (ver 4.1, Jun 2011, 2 MB)

Section II. I/O Interfaces for Arria II Devices

Chapter 6. I/O Features in Arria II Devices (ver 4.2, Dec 2011, 1 MB)
Chapter 7. External Memory Interfaces in Arria II Devices (ver 4.1, Jun 2011, 1 MB)
Chapter 8. High-Speed Differential I/O Interfaces and DPA in Arria II Devices (ver 4.2, Dec 2011, 1 MB)

Section III. System Integration for Arria II Devices

Chapter 9. Configuration, Design Security, and Remote System Upgrades in Arria II Devices (ver 4.2, Dec 2011, 1 MB)
Chapter 10. SEU Mitigation in Arria II Devices (ver 4.1, Jun 2011, 223 KB)
Chapter 11. JTAG Boundary-Scan Testing in Arria II Devices (ver 4.0, Dec 2010, 252 KB)
Chapter 12. Power Management for Arria II Devices (ver 3.1, Jun 2011, 136 KB)

Arria II Device Handbook Volume 2: Transceivers (ver 3.2, Dec 2011, 9 MB)

Section I. Transceiver Architecture for Arria II Devices

Chapter 1. Transceiver Architecture in Arria II Devices (ver 4.2, Dec 2011, 5 MB)

AN 558: Implementing Dynamic Reconfiguration in Arria II Devices

Chapter 2. Transceiver Clocking in Arria II Devices (ver 3.1, Jun 2011, 3 MB)
Chapter 3. Configuring Multiple Protocols and Data Rates in Arria II Devices (ver 3.0, Dec 2010, 430 KB)
Chapter 4. Reset Control and Power Down in Arria II Devices (ver 3.1, Jun 2011, 914 KB)

Arria II Device Handbook Volume 3: Device Datasheet and Addendum (ver 4.2, Dec 2011, 1 MB)

Section I. Device Datasheet and Addendum for Arria II Devices

Chapter 1. Device Datasheet for Arria II Devices (ver 4.2, Dec 2011, 786 KB)

Arria II I/O Timing Spreadsheet

Chapter 2. Addendum for the Arria II Device Handbook (ver 2.0, Dec 2010, 116 KB)

Related Documentation

Power and Thermal Management

Arria II GX, Arria II GZ and Arria V PowerPlay Early Power Estimator (ver 11.1 SP2, Jan 2012, 7 KB)
PowerPlay Early Power Estimator User Guide (1 MB)
Device-Specific Power Delivery Network (PDN) Tool User Guide (ver 1.0, Nov 2009, 880 KB)
     Power Delivery Network (PDN) Tool Version 11.1 for Cyclone V, Arria V, Stratix V, Cyclone IV, and Arria II GZ Devices (3 MB)
     Power Delivery Network (PDN) Tool for Arria II GX Devices (2 MB)
     Power Deliver Network (PDN) Tool for Stratix IV Devices (2 MB)
     Power Delivery Network (PDN) Tool for Stratix III Devices (2 MB)
PowerPlay Early Power Estimator User Guide (ver 6.0, Jan 2012, 2 MB)

I/O Interfaces, Protocols and Signal Integrity

AN 456: PCI Express High Performance Reference Design (ver 1.3, Sep 2010, 535 KB)
Transceiver Poster (ver 1.0, Feb 2009, 191 KB)
AN 518: SGMII Interface Implementation Using Soft-CDR Mode of Altera FPGAs (ver 2.0, Jan 2011, 821 KB)
AN 558: Implementing Dynamic Reconfiguration in Arria II Devices (ver 3.3, Nov 2011, 3 MB)
AN 635: Implementing SATA and SAS Protocols in Altera Devices (ver 1.0, Jun 2011, 584 KB)
Early SSN Estimator User Guide for Altera Programmable Devices (ver 1.0, Nov 2009, 788 KB)
Arria II GX Early SSN Estimator (387 KB)
Arria II GZ Early SSN Estimator (660 KB)
Understanding 40-nm FPGA Solutions for SATA/SAS (ver 2.0, Jul 2010, 404 KB)

DSP

Altera Product Catalog (ver 11.1, Nov 2011, 6 MB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)

Device Configuration and Remote System Upgrades

AN 603: Active Serial Remote System Upgrade Reference Design (ver 1.0, Apr 2010, 894 KB)
AN603 Design Files (1 MB)

Design Guidelines

AN 563: Design Guidelines for Arria II Devices (ver 2.0, Mar 2011, 563 KB)
AN 601: Serial Digital Interface Reference Design for Arria II GX Devices (ver 1.3, Dec 2010, 768 KB)
Design Files for AN 601 (755 KB)
AN 603: Active Serial Remote System Upgrade Reference Design (ver 1.0, Apr 2010, 894 KB)
AN603 Design Files (1 MB)
Arria II Device Family Pin Connection Guidelines (ver 1.5, Jun 2011, 306 KB)

Development Kits

Altera Product Catalog (ver 11.1, Nov 2011, 6 MB)
Arria II GX FPGA Development Board Reference Manual (ver 1.2, Mar 2011, 1 MB)
Arria II GX FPGA Development Board, 6G Edition Reference Manual (ver 1.0, Jul 2010, 1 MB)
Arria II GX FPGA Development Kit User Guide (ver 1.1, Mar 2011, 2 MB)
Arria II GX FPGA Development Kit, 6G Edition User Guide (ver 1.0, Jul 2010, 2 MB)
Video and Image Processing Solutions (ver 1.0, Apr 2011, 319 KB)

End Applications

Designing base transceiver station (BTS) channel cards with transceiver FPGAs and ASICs (ver 3.1, Jul 2010, 260 KB)
Designing military DSP applications (ver 1.0, Apr 2009, 288 KB)
Designing remote radio head applications with transceiver FPGAs (ver 2.1, Jul 2010, 262 KB)
Enabling Ethernet-Over-NG-SONET/SDH/PDH Solutions for MSPP Linecards (ver 1.0, Apr 2009, 102 KB)
FPGA companion chip solutions from Altera (ver 2.0, Nov 2010, 674 KB)
Implementing a Multirate Uncompressed Video Interface for Broadcast Applications (ver 1.1, Jul 2010, 646 KB)
Leveraging Cost-Optimized FPGAs to Deliver OTN Mapper Solutions (ver 1.0, Oct 2009, 652 KB)
Optical Transport Networks for 100G Implementation in FPGAs (ver 1.1, Jul 2010, 689 KB)
Remote Radio Heads and the Evolution Towards 4G Networks (ver 1.1, Feb 2009, 718 KB)
(Radiocomp)
Simplifying Simultaneous Multimode RRH Hardware Design (ver 1.0, Mar 2009, 1 MB)
Traffic Management Solutions from Altera (ver 1.1, Aug 2011, 366 KB)
Versatile Digital QAM Modulator (ver 2.0, Dec 2010, 553 KB)
Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
Wireless End Market Solutions (ver 4.1, Jul 2010, 144 KB)

General Device Documentation

AN 425: Using the Command-Line Jam STAPL Solution for Device Programming (ver 5.0, Dec 2010, 1,004 KB)
Innovating With a Full Spectrum of 40-nm FPGAs and ASICs With Transceivers (ver 1.4, Jul 2010, 663 KB)
Leveraging the 40-nm Process Node to Deliver the World's Most Advanced Custom Logic Devices (ver 1.1, Feb 2009, 377 KB)

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