Altera Home Page
文档资料 许可
在线购买 下载

  主页   |   产品   |   支持   |   最终市场   |   技术中心   |   教育与活动   |   公司介绍   |   在线购买  
  mySupport   |   器件   |   软件   |   IP   |   设计范例   |   参考设计  

 FPGA
      Stratix IV(E和GX)
      Stratix III
      Stratix II/Stratix II GX
      Stratix/Stratix GX
      Arria GX
      Cyclone III
      Cyclone II
      Cyclone
  
 CPLD
      MAX II
      MAX 3000A
      MAX 7000
  
 ASIC
      HardCopy III
      HardCopy II
      HardCopy Stratix
      HardCopy APEX 20K
  
 下载
      器件管脚列表
      Gerber Files
      IBIS模型
   BSDL/BST
          IEEE 1149.1
          IEEE 1532
      PCB符号
  
 配置/编程
   配置
   编程
   编程工具
  
 功耗
   功耗管理
      早期功耗估算器
      认证的电源解决方案
  
 I/O
      I/O规格
      特性
      热插拔
  
 PLL与时钟管理
      概要
      PLL基础
      在软件中使用PLL
      Jitter信息
      时钟网络
      术语
  
 封装和板级设计
      封装规格
      热阻
      布局/Socket
      制造
  
 质量与可靠性
      MSL 计算器
      认证
   环境
      PCN & Advisories
   报告
  
 失效分析
      概要
      失效分析能力
  

Download

Stratix 3 BSDL Files



Browse boundary-scan description language (BSDL) files by specific devices and choose the appropriate device package. The same BSDL file can be used regardless of speed grade or temperature.

IEEE 1149.1 Compliant Stratix III BSDL Files (1)
DevicePackageFile CodeVersion
EP3SE110 1152-pin FineLine BGA EP3SE110F1152 1.0
780-pin FineLine BGA EP3SE110F780 1.0
EP3SE260 1152-pin FineLine BGA EP3SE260F1152 1.0
1517-pin FineLine BGA EP3SE260F1517 1.0
780-pin HBGA EP3SE260H780 1.0
EP3SE50 484-pin FineLine BGA EP3SE50F484 1.0
780-pin FineLine BGA EP3SE50F780 1.0
EP3SE80 1152-pin FineLine BGA EP3SE80F1152 1.0
780-pin FineLine BGA EP3SE80F780 1.0
EP3SL110 1152-pin FineLine BGA EP3SL110F1152 1.0
780-pin FineLine BGA EP3SL110F780 1.0
EP3SL150 1152-pin FineLine BGA EP3SL150F1152 1.0
780-pin FineLine BGA EP3SL150F780 1.0
EP3SL200 1152-pin FineLine BGA EP3SL200F1152 1.0
1517-pin FineLine BGA EP3SL200F1517 1.0
780-pin HBGA EP3SL200H780 1.0
EP3SL340 1152-pin HBGA EP3SL340H1152 1.0
1517-pin FineLine BGA EP3SL340F1517 1.0
1760-pin FineLine BGA EP3SL340F1760 1.0
EP3SL50 484-pin FineLine BGA EP3SL50F484 1.0
780-pin FineLine BGA EP3SL50F780 1.0
EP3SL70 484-pin FineLine BGA EP3SL70F484 1.0
780-pin FineLine BGA EP3SL70F780 1.0

Note to Table:

  (1) The BSDL Files are syntax checked using these tools:
  1. JTAG Technologies
  2. ASSET Intertech - Agilent Technologies
  3. Corelis
  4. Goepel electronic
  5. Temento Systems

Questions or concerns about the contents of these files, can be directed to Altera's mySupport.

For information on boundary-scan testing, refer to the Related Documents links on Altera BSDL Support page.

  请填写反馈意见
  注册索取最新邮件通知