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FPGA       Stratix IV(E和GX)       Stratix III       Stratix II/Stratix II GX       Stratix/Stratix GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLD       MAX II       MAX 3000A       MAX 7000     ASIC       HardCopy III       HardCopy II       HardCopy Stratix       HardCopy APEX 20K     下载       器件管脚列表       Gerber Files       IBIS模型    BSDL/BST       PCB符号     配置/编程    配置           配置方案           指导方针           比较           特性           配置器件           解决方案           Stratix IV        Stratix III        Stratix II/Stratix II GX        Stratix/Stratix GX        Cyclone III        Cyclone II        Cyclone        APEX II        APEX 20K/E/C        Mercury        ACEX 1K                PS                JTAG                PPS                PPA        FLEX 10K/E/A    编程    编程工具     功耗    功耗管理       早期功耗估算器       认证的电源解决方案     I/O       I/O规格       特性       热插拔     PLL与时钟管理       概要       PLL基础       在软件中使用PLL       Jitter信息       时钟网络       术语     封装和板级设计       封装规格       热阻       布局/Socket       制造     质量与可靠性       MSL 计算器       认证    环境       PCN & Advisories    报告     失效分析       概要       失效分析能力

主页 > 支持 > 器件 > 配置 > ACEX 1K 打印此页 发送此页 ACEX 1K Device Family Configuration Configuration Scheme Overview The ACEX® 1K device family supports the following configuration schemes: Serial - To Conserve Pins Passive Serial (PS) Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device, or a microprocessor to control the configuration process synchronously, and supply the configuration data serially to an ACEX 1K device. JTAG Configures ACEX 1K devices via the IEEE Standard 1149.1 interface. Parallel - For Faster Configuration Passive Parallel Synchronous (PPS) Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process synchronously and supply the configuration data in a parallel manor to the ACEX 1K device. Each configuration data byte requires eight DCLK cycles. The configuration time using the PPS scheme is similar to the configuration time using the PS scheme provided the DCLK frequencies for both schemes are the same. Passive Parallel Asynchronous (PPA) Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process asynchronously and supply the configuration data in a parallel manor to the ACEX 1K device. How to Configure ACEX 1K Devices For Prototyping or Debugging Using Altera Programming Cables The Quartus® II programmer supports configuring ACEX 1K devices directly using PS or JTAG interfaces via Altera® programming cables. In the Field Using an EPC Device (PDF) The EPC device configures the ACEX 1K device automatically after power up. However, you need to program the EPC device first. MAX Series Configuration Controller Using Flash Memory (PDF) A MAX® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs. Source code (ZIP) Frequently Asked Questions If I am only configuring one FLEX 10K®, APEX™, ACEX or Mercury™ device, what should I do with the nCEO configuration pin? Can I use the Jam Standard Test and Programming Language (STAPL) or the Jam Byte-Code player to configure ACEX or FLEX devices (EP1K, EPF10K)? How many times can I reprogram or reconfigure an Altera device? Do I have to reconfigure my APEX, ACEX, or FLEX device if VCCIO goes below the device's recommended operating conditions? Can I use the EPM7064AE device configuration controller on the Nios® development board to configure FLEX and ACEX devices? What is the status of the DATA pins before and after configuration for Altera devices? For Altera devices, what is the state of the DCLK signal before and after configuration? 给本页评分

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