ACEX 1K Device Family Configuration

Configuration Scheme Overview

The ACEX^® 1K device family supports the following configuration schemes:

• Serial - To Conserve Pins
  • Passive Serial (PS)
    • Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device, or a microprocessor to control the configuration process synchronously, and supply the configuration data serially to an ACEX 1K device.
  • JTAG
    • Configures ACEX 1K devices via the IEEE Standard 1149.1 interface.
• Parallel - For Faster Configuration
  • Passive Parallel Synchronous (PPS)
    • Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process synchronously and supply the configuration data in a parallel manor to the ACEX 1K device. Each configuration data byte requires eight DCLK cycles. The configuration time using the PPS scheme is similar to the configuration time using the PS scheme provided the DCLK frequencies for both schemes are the same.
  • Passive Parallel Asynchronous (PPA)
    • Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process asynchronously and supply the configuration data in a parallel manor to the ACEX 1K device.

How to Configure ACEX 1K Devices

• For Prototyping or Debugging
  • Using Altera Programming Cables
    • The Quartus^® II programmer supports configuring ACEX 1K devices directly using PS or JTAG interfaces via Altera^® programming cables.
• In the Field
  • Using an EPC Device (PDF)
    • The EPC device configures the ACEX 1K device automatically after power up. However, you need to program the EPC device first.
  • MAX Series Configuration Controller Using Flash Memory (PDF)
    • A MAX^® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs.
    • Source code (ZIP)

Frequently Asked Questions

1. If I am only configuring one FLEX 10K^®, APEX™, ACEX or Mercury™ device, what should I do with the nCEO configuration pin?
2. Can I use the Jam Standard Test and Programming Language (STAPL) or the Jam Byte-Code player to configure ACEX or FLEX devices (EP1K, EPF10K)?
3. How many times can I reprogram or reconfigure an Altera device?
4. Do I have to reconfigure my APEX, ACEX, or FLEX device if VCCIO goes below the device's recommended operating conditions?
5. Can I use the EPM7064AE device configuration controller on the Nios^® development board to configure FLEX and ACEX devices?
6. What is the status of the DATA pins before and after configuration for Altera devices?
7. For Altera devices, what is the state of the DCLK signal before and after configuration?