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FPGA       Stratix IV(E和GX)       Stratix III       Stratix II/Stratix II GX       Stratix/Stratix GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLD       MAX II       MAX 3000A       MAX 7000     ASIC       HardCopy III       HardCopy II       HardCopy Stratix       HardCopy APEX 20K     下载       器件管脚列表       Gerber Files       IBIS模型    BSDL/BST       PCB符号     配置/编程    配置           配置方案           指导方针           比较           特性           配置器件           解决方案           Stratix IV        Stratix III        Stratix II/Stratix II GX        Stratix/Stratix GX        Cyclone III        Cyclone II        Cyclone        APEX II        APEX 20K/E/C        Mercury        ACEX 1K                PS                JTAG                PPS                PPA        FLEX 10K/E/A    编程    编程工具     功耗    功耗管理       早期功耗估算器       认证的电源解决方案     I/O       I/O规格       特性       热插拔     PLL与时钟管理       概要       PLL基础       在软件中使用PLL       Jitter信息       时钟网络       术语     封装和板级设计       封装规格       热阻       布局/Socket       制造     质量与可靠性       MSL 计算器       认证    环境       PCN & Advisories    报告     失效分析       概要       失效分析能力

主页 > 支持 > 器件 > 配置 > ACEX 1K > PS 打印此页 发送此页 ACEX 1K Device Family Passive Serial Configuration Passive Serial Configuration Passive serial (PS) configuration can be performed using an Altera® download cable, an Altera configuration device, or an intelligent host such as a microprocessor or a MAX® or MAX II CPLD. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to an ACEX® 1K device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle. Configuration Methods in Passive Serial Mode Using a configuration device Using a microprocessor Using a download cable For more information, please refer to the Configuring Mercury, APEX 20K (2.5 V), ACEX 1K & FLEX 10K Devices chapter in the Configuration Handbook. Embedded Solution MicroBlasterTM Portable software driver used to configure an FPGA via a PS interface Works on a PC using a ByteBlasterTM II or ByteBlasterMVTM download cable Source code available for porting to an embedded or other platform MicorBlaster Embedded Version Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board white paper Source code available for reference purpose Reference Design MAX Series Configuration Controller Using Flash Memory Using a MAX or MAX II device as a configuration controller to configure an Altera FPGA from flash memory Source code in Verilog and VHDL Related Literature Altera Configuration Devices Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet 给本页评分

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