APEX II Fast Passive Parallel Configuration

Fast Passive Parallel Configuration

To meet the continuously increasing demand for faster configuration times, APEX^TM II devices offer fast passive parallel (FPP) configuration. APEX II devices have the capability of receiving byte-wide configuration data every clock cycle.

Configuration Methods in FPP Mode

• Using an enhanced configuration device
• Using a microprocessor or CPLD

For more information, please refer to the Configuring APEX II Devices chapter in the Configuration Handbook.

Embedded Solution

• Configuring the MicroBlaster^TM Fast Passive Parallel Software Driver
  • Portable software driver used to configure an FPGA via an FPP interface
  • Source code available for porting to an embedded or other platform

Reference Design

• MAX Series Configuration Controller Using Flash Memory
  • Using a MAX^® or MAX II device as a configuration controller to configure Altera^® FPGAs from flash memory
  • Source code in Verilog and VHDL

Related Literature

• Altera Configuration Devices
• Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet