APEX 20K Device Family Configuration

Configuration Scheme Overview

The APEX^TM 20K device family supports the following configuration schemes:

• Serial - To Conserve Pins 
  • Passive Serial (PS)
    • Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device (PDF), or a microprocessor to control the configuration process synchronously and supply the configuration data serially to an APEX 20K, APEX 20KE, or APEX 20KC device.
  • JTAG
    • Configures APEX 20K, APEX 20KE, or APEX 20KC devices via the IEEE Standard 1149.1 interface.
• Parallel - For Faster Configuration
  • Passive Parallel Synchronous (PPS)
    • Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process synchronously and supply the configuration data in a parallel manor to the APEX 20K, APEX 20KE or APEX 20KC device. Each configuration data byte requires eight DCLK cycles. The configuration time using the PPS scheme is similar to the configuration time using a PS scheme provided the DCLK frequencies for both schemes are the same.
  • Passive Parallel Asynchronous (PPA)
    • Uses an external intelligent host, such as a PC or microprocessor, to control the configuration process asynchronously and supply the configuration data in a parallel manor to the APEX 20K, APEX 20KE, or APEX 20KC device.

How to Configure APEX 20K Devices

• For Prototyping or Debugging
  • Using Altera Programming Cables
    • The Quartus^® II programmer supports configuring APEX 20K, APEX 20KE, and APEX 20KC devices directly using PS or JTAG interfaces via Altera^® programming cables.
• In the Field 
  • Using an EPC Device (PDF)
    • The EPC device configures the APEX 20K, APEX 20KE, or APEX 20KC device automatically after power up. However, you need to program the EPC device first.
  • MAX Series Configuration Controller Using Flash Memory (PDF)
    • A MAX^® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs
    • Source code (ZIP)

Frequently Asked Questions

1. What happens to the nCEO pin if I configure my APEX 20K or FLEX^® 10K device in JTAG mode?
2. Which Altera devices have internal oscillators that are active during normal device operation?
3. What is the state of APEX 20K or FLEX 10K registers if the DEV_CLRn pin is left floating?
4. Do APEX 20KE and 20KC devices have the same JTAG ID code?
5. Does the EPC16 configuration device support fast passive parallel (8-bit parallel) configuration for a single FLEX, ACEX^®, APEX, or APEX II device?
6. What is the ByteBlaster™ II download cable?
7. Can I use an APEX or FLEX I/O pin to drive nCONFIG low, allowing me to start the reconfiguration of my FLEX device?
8. Why is CONF_DONE never driving low on power-up, and/or why is the device drawing excessive power in an APEX 20KE device?
9. Can I configure an APEX 20K or FLEX 10K device with an EPC1064 or EPC1213 configuration device?
10. What is the alignment of the flash address pins A(20:0) on the APEX EPC16 device?
11. When does each APEX 20K or FLEX 10K device initialize when configured in a multi-device JTAG chain?
12. How should I connect my unused APEX 20K or APEX 20KE I/O pins?
13. What are the I/O characteristics of an unconfigured APEX 20KE or Mercury^TM device during boundary-scan test (BST)?
14. Do I need to generate a new Programmer Object File (.pof) when I transfer my APEX 20K design to a 5.0-V tolerant APEX 20K device?