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主页 > 支持 > 器件 > 配置 > 特性 打印此页 发送此页 Configuration Features For a summary of the configuration features supported by each Altera® FPGA family, refer to Table 1. Table 1. Configuration Features Supported by Altera FPGAs Device Decompression Support Design Security Support Remote System Upgrade Support Stratix® IV Stratix III Stratix II and Stratix II GX Stratix and Stratix GX     Cyclone® III   Cyclone II     Cyclone     APEXTM II       APEX 20K, 20KE, and 20KC       MercuryTM       ACEX® 1K       FLEX 10K®, 10KE, and 10KA       Decompression Support Some Altera devices support configuration data decompression, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to the device. During configuration, the device decompresses the bitstream in real time and configures its SRAM cells. Refer to the configuration chapter of the respective Altera FPGA in the Configuration Handbook for more information. Design Security Support Some Altera devices can decrypt a configuration bitstream using the advanced encryption standard (AES) algorithm—the most advanced encryption algorithm available today. When using the design security feature, a security key is stored in the FPGA. To successfully configure an FPGA that has the design security feature enabled, you must configure the device with a configuration file that was encrypted using the same security key. The security key can be stored in non-volatile memory inside the device. This non-volatile memory does not require any external devices, such as a battery back-up, for storage. Refer to the configuration chapter of the respective Altera device in the Configuration Handbook for more information. AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices (PDF) AN512: Using the Design Security Feature in Stratix III Devices (PDF) Remote System Upgrade Support Some Altera devices have dedicated remote system upgrade circuitry. Soft logic (either the Nios® II embedded processor or user logic) implemented in the device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry helps to avoid system downtime. Refer to the configuration chapter of the respective Altera device in the Configuration Handbook for more information. Remote System Upgrades with Stratix Devices altremote_update Megafunction User Guide (PDF) Back to Configuration Guide page 给本页评分   相关链接 Configuration Guidelines     注册索取最新邮件通知

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