Cyclone Device Configuration

Configuration Scheme Overview

Cyclone^TM devices support the following configuration schemes:

• Serial - To Conserve Pins
  • Active Serial (AS)
    • Uses the Cyclone device to control the configuration process and get the configuration data from a serial configuration (EPCS) device (PDF).
  • Passive Serial (PS)
    • Uses an external intelligent host such as a PC, an enhanced configuration (EPC) device (PDF) or a microprocessor to control the configuration process synchronously and supply the configuration data serially to a Cyclone device.
  • JTAG
    • Configures Cyclone devices via the IEEE 1149.1 Standard interface. 

How to Configure Cyclone Devices

• For Prototyping or Debugging
  • Using Altera Programming Cables
    • The Quartus^® II programmer supports configuring Cyclone devices directly using PS or JTAG interfaces via Altera^® programming cables.
• In the Field
  • Using an EPCS Device (PDF)
    • The Cyclone device gets its configuration data from the EPCS device automatically after power up. However, you need to program the EPCS device first.
  • Using an EPC Device (PDF)
    • The EPC device configures the Cyclone device automatically after power up. However, you need to program the EPC device first.
  • MAX Series Configuration Controller Using Flash Memory (PDF)
    • A MAX^® or MAX II device is used as a flash memory configuration controller to configure Altera FPGAs.
    • Source code (ZIP)

Frequently Asked Questions

1. What is the status of the I/O pins if the VCCIO of the I/O banks in which these pins reside is not applied during configuration for Stratix^® II, Stratix and Cyclone devices?
2. What solutions does Altera offer for soft-error/SEU mitigation?
3. Do I need a pull-up resistor on the DATA configuration input signal of my Stratix, Stratix GX, or Cyclone device?
4. Which Altera devices have internal oscillators that are active during normal device operation?
5. Does the static supply current for Stratix, Stratix GX and Cyclone devices differ before and after configuration?
6. What is the value of the internal weak pull-up resistors for the AS configuration pins (DATA0, DCLK, nCSO and ASDO), when the Cyclone device is set in AS mode (MSEL[1:0] = 2'b00)?
7. Which of the Altera devices support CONFIG_IO Instruction?
8. What is a serial configuration (EPCS) device?
9. Can you cascade EPCS devices?
10. What input file should be used to program a EPCS?
11. How many times can I program and erase the serial configuration devices (EPCS1 and EPCS4)?
12. Is it acceptable to toggle the DATA and DCLK signals once a Stratix or a Cyclone device has entered user mode?
13. What is CONFIG_IO?
14. Can you set the power-on reset time (POR) in Cyclone devices?
15. Do I need to power the VCCIO of every IO bank in my Stratix, Stratix GX, Cyclone, or APEX^TM II device in order to have a successful configuration?
16. Do I need to make any change to the Raw Binary File (.rbf) when I use JRunner to configure Cyclone devices?
17. What are the considerations when configuring Cyclone EP1C6 using JTAG-based configuration?
18. How can I create a compressed configuration bitstream to take advantage of the Cyclone FPGA's on-chip decompression feature?
19. The option "Auto-restart configuration after error" is available for AS mode according to the datasheet. However, if you search for this feature in Quartus II version 4.2 SP1 help, it says it only applies to PS mode. Which is correct?
20. Why does configuration behavior for an Altera FPGA device behave differently with Quartus II software versions 4.1 and 4.2 if there is an configuration device that will perform configuration if nCONFIG is toggled?