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FPGA       Stratix IV(E和GX)       Stratix III       Stratix II/Stratix II GX       Stratix/Stratix GX       Arria GX       Cyclone III       Cyclone II       Cyclone     CPLD       MAX II       MAX 3000A       MAX 7000     ASIC       HardCopy III       HardCopy II       HardCopy Stratix       HardCopy APEX 20K     下载       器件管脚列表       Gerber Files       IBIS模型    BSDL/BST       PCB符号     配置/编程    配置           配置方案           指导方针           比较           特性           配置器件           解决方案           Stratix IV        Stratix III        Stratix II/Stratix II GX        Stratix/Stratix GX        Cyclone III                PS                AP                AS                JTAG                FPP                PPA        Cyclone II        Cyclone        APEX II        APEX 20K/E/C        Mercury        ACEX 1K        FLEX 10K/E/A    编程    编程工具     功耗    功耗管理       早期功耗估算器       认证的电源解决方案     I/O       I/O规格       特性       热插拔     PLL与时钟管理       概要       PLL基础       在软件中使用PLL       Jitter信息       时钟网络       术语     封装和板级设计       封装规格       热阻       布局/Socket       制造     质量与可靠性       MSL 计算器       认证    环境       PCN & Advisories    报告     失效分析       概要       失效分析能力

主页 > 支持 > 器件 > 配置 > Cyclone III > PS 打印此页 发送此页 Cyclone III Device Passive Serial Configuration You can perform passive serial (PS) configuration using an Altera® download cable, or an intelligent host such as a microprocessor, or a MAX® or MAX II CPLD. During PS configuration, data is transferred from a flash memory, or other storage device to the Cyclone® III device on the DATA[0] pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle. The maximum DCLK frequency supported by the Cyclone III device is 100 MHz. Configuration Methods in Passive Serial Mode include: Using a download cable for in-system programmability (ISP) and prototyping Using a MAX II device as an external host Using a microprocessor For more information, please refer to the Configuring Cyclone III Devices chapter of the Configuration Handbook. Embedded Solution MicroBlasterTM Software Driver Please refer to the AN 423: Configuring the MicroBlaster Passive Serial Software Driver white paper (PDF) Portable software driver used to configure an FPGA via a PS interface Works on a PC using a ByteBlasterTM II or ByteBlasterMVTM download cable Source code (ZIP) available for porting to an embedded or other platform MicroBlaster Embedded Version Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board (PDF) white paper Source code (ZIP) available for porting to an embedded or other platform Reference Design MAX Series Configuration Controller Using Flash Memory (PDF) Using a MAX or MAX II device as a configuration controller to configure Altera FPGAs from flash memory Source code (ZIP) in Verilog and VHDL 给本页评分

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