Stratix II/Stratix II GX Device JTAG Configuration

JTAG Configuration

The JTAG configuration scheme uses the IEEE Standard 1149.1 JTAG interface pins and supports the JAM Standard Test and Programming Language (STAPL) standard. Stratix^® II/Stratix II GX devices are designed such that JTAG instructions have precedence over any device configuration mode. Therefore, JTAG configuration can take place without waiting for other configuration modes to complete. JTAG configuration can be performed using an Altera^® download cable or an intelligent host, such as a microprocessor.

Configuration Method in JTAG Mode

• Using a download cable for in-system programmability (ISP) and prototyping

For more information, please refer to the Configuring Stratix II & Stratix II GX Devices chapter in the Configuration Handbook.

Embedded Solution

• JRunner
  • Portable software driver used to configure an FPGA via a JTAG interface
  • Works on a PC using a ByteBlaster^TM II or ByteBlasterMV^TM download cable
  • Source code available for porting to an embedded or other platform for Stratix II devices
  • Currently the JRunner source code support for Stratix II GX devices is not yet available

Related Literature

• IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II & Stratix II GX Devices
• AN 39: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices