Passive Serial Configuration
Passive serial (PS) configuration can be performed using an Altera® download cable, an Altera configuration device, or an intelligent host such as a microprocessor. During PS configuration, data is transferred from a configuration device, flash memory, or other storage device to the Stratix® II/Stratix II GX device on the DATA0 pin. This configuration data is latched into the FPGA on the rising edge of DCLK. Configuration data is transferred at a rate of one bit per clock cycle.
Configuration Methods in Passive Serial Mode
- Using a download cable for in-system programmability (ISP) and prototyping
- Using a configuration device
- Using a MAX® II device as an external host
- Using a microprocessor
For more information, please refer to the Configuring Stratix II & Stratix II GX Devices chapter in the Configuration Handbook.
Embedded Solution
- MicroBlasterTM
- Portable software driver used to configure an FPGA via a PS interface
- Works on a PC using a ByteBlasterTM II or ByteBlasterMVTM download cable
- Source code available for porting to an embedded or other platform
- MicroBlaster Embedded Version
- Please refer to the Implementing the MicroBlaster Configuration on the ColdFire Development Board white paper
- Source code available for porting to an embedded or other platform
Reference Design
- MAX Series Configuration Controller Using Flash Memory
- Using a MAX or MAX II device as a configuration controller to configure Altera FPGAs from flash memory
- Source code in Verilog and VHDL
